`timescale 1 ps/ 1 ps

module example_board(
	PIN_16,
	PIN_23,
	PIN_24,
	PIN_25,
	PIN_26,
	PIN_33,
	PIN_34,
	PIN_35,
	PIN_36,
	PIN_37,
	PIN_38,
	PIN_39,
	PIN_40,
	PIN_41,
	PIN_42,
	PIN_43,
	PIN_44,
	PIN_45,
	PIN_47,
	PIN_52,
	PIN_53,
	PIN_54,
	PIN_55,
	PIN_56,
	PIN_57,
	PIN_58,
	PIN_HSE,
	PIN_HSI,
	PIN_OSC);
inout	PIN_16;
inout	PIN_23;
output	PIN_24;
inout	PIN_25;
inout	PIN_26;
inout	PIN_33;
output	PIN_34;
inout	PIN_35;
inout	PIN_36;
inout	PIN_37;
inout	PIN_38;
inout	PIN_39;
inout	PIN_40;
inout	PIN_41;
output	PIN_42;
inout	PIN_43;
output	PIN_44;
inout	PIN_45;
inout	PIN_47;
output	PIN_52;
input	PIN_53;
inout	PIN_54;
output	PIN_55;
output	PIN_56;
output	PIN_57;
input	PIN_58;
input	PIN_HSE;
input	PIN_HSI;
input	PIN_OSC;

//wire	gnd;
//wire	vcc;
wire	AsyncReset_X49_Y2_GND;
wire	AsyncReset_X50_Y2_GND;
wire	AsyncReset_X51_Y1_GND;
wire	AsyncReset_X52_Y1_GND;
wire	AsyncReset_X52_Y2_GND;
wire	AsyncReset_X53_Y1_GND;
wire	AsyncReset_X53_Y2_GND;
wire	AsyncReset_X54_Y1_GND;
wire	AsyncReset_X54_Y2_GND;
wire	AsyncReset_X56_Y1_GND;
wire	AsyncReset_X56_Y2_GND;
wire	AsyncReset_X57_Y2_GND;
wire	AsyncReset_X58_Y2_GND;
wire	AsyncReset_X59_Y2_GND;
wire	\PIN_16~input_o ;
wire	\PIN_23~input_o ;
wire	\PIN_25~input_o ;
wire	\PIN_26~input_o ;
wire	\PIN_33~input_o ;
wire	\PIN_35~input_o ;
wire	\PIN_36~input_o ;
wire	\PIN_37~input_o ;
wire	\PIN_38~input_o ;
wire	\PIN_39~input_o ;
wire	\PIN_40~input_o ;
wire	\PIN_41~input_o ;
wire	\PIN_43~input_o ;
wire	\PIN_45~input_o ;
wire	\PIN_47~input_o ;
wire	\PIN_53~input_o ;
wire	\PIN_54~input_o ;
wire	\PIN_58~input_o ;
wire	\PIN_HSE~input_o ;
wire	\PIN_HSI~input_o ;
wire	\PIN_OSC~input_o ;
wire	\PLL_ENABLE~clkctrl_outclk ;
wire	\PLL_ENABLE~clkctrl_outclk__AsyncReset_X48_Y2_SIG ;
wire	\PLL_ENABLE~combout ;
wire	\PLL_LOCK~combout ;
wire	SyncLoad_X49_Y2_VCC;
wire	SyncLoad_X50_Y2_VCC;
wire	SyncLoad_X51_Y1_VCC;
wire	SyncLoad_X52_Y1_VCC;
wire	SyncLoad_X52_Y2_VCC;
wire	SyncLoad_X53_Y1_VCC;
wire	SyncLoad_X53_Y2_VCC;
wire	SyncLoad_X54_Y1_VCC;
wire	SyncLoad_X54_Y2_VCC;
wire	SyncLoad_X56_Y1_VCC;
wire	SyncLoad_X56_Y2_VCC;
wire	SyncLoad_X57_Y2_VCC;
wire	SyncLoad_X58_Y2_VCC;
wire	SyncReset_X49_Y2_GND;
wire	SyncReset_X50_Y2_GND;
wire	SyncReset_X51_Y1_GND;
wire	SyncReset_X52_Y1_GND;
wire	SyncReset_X52_Y2_GND;
wire	SyncReset_X53_Y1_GND;
wire	SyncReset_X53_Y2_GND;
wire	SyncReset_X54_Y1_GND;
wire	SyncReset_X54_Y2_GND;
wire	SyncReset_X56_Y1_GND;
wire	SyncReset_X56_Y2_GND;
wire	SyncReset_X57_Y2_GND;
wire	SyncReset_X58_Y2_GND;
wire	\auto_generated_inst.hbo_13_7ba00b93ceceb4ca_bp ;
wire	\auto_generated_inst.hbo_13_7ba00b93ceceb4ca_bp_X48_Y2_SIG_VCC ;
wire	\auto_generated_inst.hbo_22_7da7c782f7e09fdc_bp ;
wire	\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ;
wire	\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X52_Y2_SIG_VCC ;
wire	\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X51_Y2_SIG_SIG ;
tri1	devclrn;
tri1	devoe;
tri1	devpor;
wire	[3:0] ext_dma_DMACBREQ;
//wire	ext_dma_DMACBREQ[0];
//wire	ext_dma_DMACBREQ[1];
//wire	ext_dma_DMACBREQ[2];
//wire	ext_dma_DMACBREQ[3];
wire	[3:0] ext_dma_DMACLBREQ;
//wire	ext_dma_DMACLBREQ[0];
//wire	ext_dma_DMACLBREQ[1];
//wire	ext_dma_DMACLBREQ[2];
//wire	ext_dma_DMACLBREQ[3];
wire	[3:0] ext_dma_DMACLSREQ;
//wire	ext_dma_DMACLSREQ[0];
//wire	ext_dma_DMACLSREQ[1];
//wire	ext_dma_DMACLSREQ[2];
//wire	ext_dma_DMACLSREQ[3];
wire	[3:0] ext_dma_DMACSREQ;
//wire	ext_dma_DMACSREQ[0];
//wire	ext_dma_DMACSREQ[1];
//wire	ext_dma_DMACSREQ[2];
//wire	ext_dma_DMACSREQ[3];
wire	\gclksw_inst|gclk_switch__alta_gclksw__clkout ;
wire	[7:0] gpio1_io_in;
//wire	gpio1_io_in[0];
//wire	gpio1_io_in[1];
//wire	gpio1_io_in[2];
//wire	gpio1_io_in[3];
//wire	gpio1_io_in[4];
//wire	gpio1_io_in[5];
//wire	gpio1_io_in[6];
//wire	gpio1_io_in[7];
wire	[7:0] gpio2_io_in;
//wire	gpio2_io_in[0];
//wire	gpio2_io_in[1];
//wire	gpio2_io_in[2];
//wire	gpio2_io_in[3];
//wire	gpio2_io_in[4];
//wire	gpio2_io_in[5];
//wire	gpio2_io_in[6];
//wire	gpio2_io_in[7];
wire	[7:0] gpio3_io_in;
//wire	gpio3_io_in[0];
//wire	gpio3_io_in[1];
//wire	gpio3_io_in[2];
//wire	gpio3_io_in[3];
//wire	gpio3_io_in[4];
//wire	gpio3_io_in[5];
//wire	gpio3_io_in[6];
//wire	gpio3_io_in[7];
wire	[7:0] gpio3_io_out_data;
//wire	gpio3_io_out_data[0];
//wire	gpio3_io_out_data[1];
//wire	gpio3_io_out_data[2];
//wire	gpio3_io_out_data[3];
//wire	gpio3_io_out_data[4];
//wire	gpio3_io_out_data[5];
//wire	gpio3_io_out_data[6];
//wire	gpio3_io_out_data[7];
wire	[7:0] gpio3_io_out_en;
//wire	gpio3_io_out_en[0];
//wire	gpio3_io_out_en[1];
//wire	gpio3_io_out_en[2];
//wire	gpio3_io_out_en[3];
//wire	gpio3_io_out_en[4];
//wire	gpio3_io_out_en[5];
//wire	gpio3_io_out_en[6];
//wire	gpio3_io_out_en[7];
wire	[7:0] gpio4_io_in;
//wire	gpio4_io_in[0];
//wire	gpio4_io_in[1];
//wire	gpio4_io_in[2];
//wire	gpio4_io_in[3];
//wire	gpio4_io_in[4];
//wire	gpio4_io_in[5];
//wire	gpio4_io_in[6];
//wire	gpio4_io_in[7];
wire	[7:0] gpio4_io_out_data;
//wire	gpio4_io_out_data[0];
//wire	gpio4_io_out_data[1];
//wire	gpio4_io_out_data[2];
//wire	gpio4_io_out_data[3];
//wire	gpio4_io_out_data[4];
//wire	gpio4_io_out_data[5];
//wire	gpio4_io_out_data[6];
//wire	gpio4_io_out_data[7];
wire	[7:0] gpio4_io_out_en;
//wire	gpio4_io_out_en[0];
//wire	gpio4_io_out_en[1];
//wire	gpio4_io_out_en[2];
//wire	gpio4_io_out_en[3];
//wire	gpio4_io_out_en[4];
//wire	gpio4_io_out_en[5];
//wire	gpio4_io_out_en[6];
//wire	gpio4_io_out_en[7];
wire	[7:0] gpio5_io_in;
//wire	gpio5_io_in[0];
//wire	gpio5_io_in[1];
//wire	gpio5_io_in[2];
//wire	gpio5_io_in[3];
//wire	gpio5_io_in[4];
//wire	gpio5_io_in[5];
//wire	gpio5_io_in[6];
//wire	gpio5_io_in[7];
wire	[7:0] gpio5_io_out_data;
//wire	gpio5_io_out_data[0];
//wire	gpio5_io_out_data[1];
//wire	gpio5_io_out_data[2];
//wire	gpio5_io_out_data[3];
//wire	gpio5_io_out_data[4];
//wire	gpio5_io_out_data[5];
//wire	gpio5_io_out_data[6];
//wire	gpio5_io_out_data[7];
wire	[7:0] gpio5_io_out_en;
//wire	gpio5_io_out_en[0];
//wire	gpio5_io_out_en[1];
//wire	gpio5_io_out_en[2];
//wire	gpio5_io_out_en[3];
//wire	gpio5_io_out_en[4];
//wire	gpio5_io_out_en[5];
//wire	gpio5_io_out_en[6];
//wire	gpio5_io_out_en[7];
wire	[7:0] gpio6_io_in;
//wire	gpio6_io_in[0];
//wire	gpio6_io_in[1];
//wire	gpio6_io_in[2];
//wire	gpio6_io_in[3];
//wire	gpio6_io_in[4];
//wire	gpio6_io_in[5];
//wire	gpio6_io_in[6];
//wire	gpio6_io_in[7];
wire	[7:0] gpio6_io_out_data;
//wire	gpio6_io_out_data[0];
//wire	gpio6_io_out_data[1];
//wire	gpio6_io_out_data[2];
//wire	gpio6_io_out_data[3];
//wire	gpio6_io_out_data[4];
//wire	gpio6_io_out_data[5];
//wire	gpio6_io_out_data[6];
//wire	gpio6_io_out_data[7];
wire	[7:0] gpio6_io_out_en;
//wire	gpio6_io_out_en[0];
//wire	gpio6_io_out_en[1];
//wire	gpio6_io_out_en[2];
//wire	gpio6_io_out_en[3];
//wire	gpio6_io_out_en[4];
//wire	gpio6_io_out_en[5];
//wire	gpio6_io_out_en[6];
//wire	gpio6_io_out_en[7];
wire	[7:0] gpio7_io_in;
//wire	gpio7_io_in[0];
//wire	gpio7_io_in[1];
//wire	gpio7_io_in[2];
//wire	gpio7_io_in[3];
//wire	gpio7_io_in[4];
//wire	gpio7_io_in[5];
//wire	gpio7_io_in[6];
//wire	gpio7_io_in[7];
wire	[7:0] gpio7_io_out_data;
//wire	gpio7_io_out_data[0];
//wire	gpio7_io_out_data[1];
//wire	gpio7_io_out_data[2];
//wire	gpio7_io_out_data[3];
//wire	gpio7_io_out_data[4];
//wire	gpio7_io_out_data[5];
//wire	gpio7_io_out_data[6];
//wire	gpio7_io_out_data[7];
wire	[7:0] gpio7_io_out_en;
//wire	gpio7_io_out_en[0];
//wire	gpio7_io_out_en[1];
//wire	gpio7_io_out_en[2];
//wire	gpio7_io_out_en[3];
//wire	gpio7_io_out_en[4];
//wire	gpio7_io_out_en[5];
//wire	gpio7_io_out_en[6];
//wire	gpio7_io_out_en[7];
wire	[7:0] gpio8_io_in;
//wire	gpio8_io_in[0];
//wire	gpio8_io_in[1];
//wire	gpio8_io_in[2];
//wire	gpio8_io_in[3];
//wire	gpio8_io_in[4];
//wire	gpio8_io_in[5];
//wire	gpio8_io_in[6];
//wire	gpio8_io_in[7];
wire	[7:0] gpio9_io_in;
//wire	gpio9_io_in[0];
//wire	gpio9_io_in[1];
//wire	gpio9_io_in[2];
//wire	gpio9_io_in[3];
//wire	gpio9_io_in[4];
//wire	gpio9_io_in[5];
//wire	gpio9_io_in[6];
//wire	gpio9_io_in[7];
wire	hbi_272_0_9cb2c0024f9919c5_bp;
wire	hbi_272_1_9cb2c0024f9919c5_bp;
wire	[3:0] local_int;
//wire	local_int[0];
//wire	local_int[1];
//wire	local_int[2];
//wire	local_int[3];
wire	\macro_inst|ahb2apb_inst|Selector0~0_combout ;
wire	\macro_inst|ahb2apb_inst|Selector25~0_combout ;
wire	\macro_inst|ahb2apb_inst|always0~0_combout ;
wire	\macro_inst|ahb2apb_inst|always2~0_combout ;
wire	\macro_inst|ahb2apb_inst|apbState.apbIdle~q ;
wire	\macro_inst|ahb2apb_inst|apbState.apbSetup~q ;
wire	\macro_inst|ahb2apb_inst|comb~0_combout ;
wire	[15:0] \macro_inst|ahb2apb_inst|haddr ;
//wire	\macro_inst|ahb2apb_inst|haddr [0];
//wire	\macro_inst|ahb2apb_inst|haddr [10];
//wire	\macro_inst|ahb2apb_inst|haddr [11];
//wire	\macro_inst|ahb2apb_inst|haddr [12];
//wire	\macro_inst|ahb2apb_inst|haddr [13];
//wire	\macro_inst|ahb2apb_inst|haddr [14];
//wire	\macro_inst|ahb2apb_inst|haddr [15];
wire	\macro_inst|ahb2apb_inst|haddr[15]__feeder__LutOut ;
//wire	\macro_inst|ahb2apb_inst|haddr [1];
//wire	\macro_inst|ahb2apb_inst|haddr [2];
//wire	\macro_inst|ahb2apb_inst|haddr [3];
//wire	\macro_inst|ahb2apb_inst|haddr [4];
//wire	\macro_inst|ahb2apb_inst|haddr [5];
//wire	\macro_inst|ahb2apb_inst|haddr [6];
//wire	\macro_inst|ahb2apb_inst|haddr [7];
//wire	\macro_inst|ahb2apb_inst|haddr [8];
//wire	\macro_inst|ahb2apb_inst|haddr [9];
wire	\macro_inst|ahb2apb_inst|hdone~0_combout ;
wire	\macro_inst|ahb2apb_inst|hdone~q ;
wire	\macro_inst|ahb2apb_inst|hreadyout~0_combout ;
wire	\macro_inst|ahb2apb_inst|hreadyout~q ;
wire	\macro_inst|ahb2apb_inst|hwrite__feeder__LutOut ;
wire	\macro_inst|ahb2apb_inst|hwrite~q ;
wire	[15:0] \macro_inst|ahb2apb_inst|paddr ;
//wire	\macro_inst|ahb2apb_inst|paddr [0];
//wire	\macro_inst|ahb2apb_inst|paddr [10];
//wire	\macro_inst|ahb2apb_inst|paddr [11];
//wire	\macro_inst|ahb2apb_inst|paddr [12];
//wire	\macro_inst|ahb2apb_inst|paddr [13];
//wire	\macro_inst|ahb2apb_inst|paddr [14];
//wire	\macro_inst|ahb2apb_inst|paddr [15];
wire	\macro_inst|ahb2apb_inst|paddr[15]~feeder_combout ;
//wire	\macro_inst|ahb2apb_inst|paddr [1];
//wire	\macro_inst|ahb2apb_inst|paddr [2];
//wire	\macro_inst|ahb2apb_inst|paddr [3];
//wire	\macro_inst|ahb2apb_inst|paddr [4];
//wire	\macro_inst|ahb2apb_inst|paddr [5];
//wire	\macro_inst|ahb2apb_inst|paddr [6];
//wire	\macro_inst|ahb2apb_inst|paddr [7];
//wire	\macro_inst|ahb2apb_inst|paddr [8];
//wire	\macro_inst|ahb2apb_inst|paddr [9];
wire	\macro_inst|ahb2apb_inst|pdone~0_combout ;
wire	\macro_inst|ahb2apb_inst|pdone~q ;
wire	\macro_inst|ahb2apb_inst|penable~q ;
wire	[31:0] \macro_inst|ahb2apb_inst|prdata ;
//wire	\macro_inst|ahb2apb_inst|prdata [0];
//wire	\macro_inst|ahb2apb_inst|prdata [10];
//wire	\macro_inst|ahb2apb_inst|prdata [11];
//wire	\macro_inst|ahb2apb_inst|prdata [12];
//wire	\macro_inst|ahb2apb_inst|prdata [13];
//wire	\macro_inst|ahb2apb_inst|prdata [14];
//wire	\macro_inst|ahb2apb_inst|prdata [15];
//wire	\macro_inst|ahb2apb_inst|prdata [16];
//wire	\macro_inst|ahb2apb_inst|prdata [17];
//wire	\macro_inst|ahb2apb_inst|prdata [18];
//wire	\macro_inst|ahb2apb_inst|prdata [19];
//wire	\macro_inst|ahb2apb_inst|prdata [1];
//wire	\macro_inst|ahb2apb_inst|prdata [20];
//wire	\macro_inst|ahb2apb_inst|prdata [21];
//wire	\macro_inst|ahb2apb_inst|prdata [22];
//wire	\macro_inst|ahb2apb_inst|prdata [23];
//wire	\macro_inst|ahb2apb_inst|prdata [24];
//wire	\macro_inst|ahb2apb_inst|prdata [25];
//wire	\macro_inst|ahb2apb_inst|prdata [26];
//wire	\macro_inst|ahb2apb_inst|prdata [27];
//wire	\macro_inst|ahb2apb_inst|prdata [28];
//wire	\macro_inst|ahb2apb_inst|prdata [29];
//wire	\macro_inst|ahb2apb_inst|prdata [2];
//wire	\macro_inst|ahb2apb_inst|prdata [30];
//wire	\macro_inst|ahb2apb_inst|prdata [31];
//wire	\macro_inst|ahb2apb_inst|prdata [3];
//wire	\macro_inst|ahb2apb_inst|prdata [4];
//wire	\macro_inst|ahb2apb_inst|prdata [5];
//wire	\macro_inst|ahb2apb_inst|prdata [6];
//wire	\macro_inst|ahb2apb_inst|prdata [7];
//wire	\macro_inst|ahb2apb_inst|prdata [8];
//wire	\macro_inst|ahb2apb_inst|prdata [9];
wire	\macro_inst|ahb2apb_inst|psel~0_combout ;
wire	\macro_inst|ahb2apb_inst|psel~q ;
wire	\macro_inst|ahb2apb_inst|pvalid~q ;
wire	\macro_inst|ahb2apb_inst|pwrite~0_combout ;
wire	\macro_inst|ahb2apb_inst|pwrite~feeder_combout ;
wire	\macro_inst|ahb2apb_inst|pwrite~q ;
wire	\macro_inst|always1~0_combout ;
wire	\macro_inst|always3~0_combout ;
wire	\macro_inst|always5~0_combout ;
wire	[31:0] \macro_inst|apb_prdata ;
//wire	\macro_inst|apb_prdata [0];
//wire	\macro_inst|apb_prdata [10];
//wire	\macro_inst|apb_prdata [11];
//wire	\macro_inst|apb_prdata [12];
//wire	\macro_inst|apb_prdata [13];
//wire	\macro_inst|apb_prdata [14];
//wire	\macro_inst|apb_prdata [15];
//wire	\macro_inst|apb_prdata [16];
//wire	\macro_inst|apb_prdata [17];
//wire	\macro_inst|apb_prdata [18];
//wire	\macro_inst|apb_prdata [19];
//wire	\macro_inst|apb_prdata [1];
//wire	\macro_inst|apb_prdata [20];
//wire	\macro_inst|apb_prdata [21];
//wire	\macro_inst|apb_prdata [22];
//wire	\macro_inst|apb_prdata [23];
//wire	\macro_inst|apb_prdata [24];
//wire	\macro_inst|apb_prdata [25];
//wire	\macro_inst|apb_prdata [26];
//wire	\macro_inst|apb_prdata [27];
//wire	\macro_inst|apb_prdata [28];
//wire	\macro_inst|apb_prdata [29];
//wire	\macro_inst|apb_prdata [2];
//wire	\macro_inst|apb_prdata [30];
//wire	\macro_inst|apb_prdata [31];
//wire	\macro_inst|apb_prdata [3];
//wire	\macro_inst|apb_prdata [4];
//wire	\macro_inst|apb_prdata [5];
//wire	\macro_inst|apb_prdata [6];
//wire	\macro_inst|apb_prdata [7];
//wire	\macro_inst|apb_prdata [8];
//wire	\macro_inst|apb_prdata [9];
wire	\macro_inst|apb_prdata~0_combout ;
wire	\macro_inst|apb_prdata~1_combout ;
wire	\macro_inst|apb_prdata~2_combout ;
wire	\macro_inst|apb_prdata~3_combout ;
wire	\macro_inst|apb_prdata~4_combout ;
wire	\macro_inst|apb_prdata~5_combout ;
wire	\macro_inst|apb_prdata~6_combout ;
wire	\macro_inst|apb_prdata~7_combout ;
wire	\macro_inst|apb_prdata~8_combout ;
wire	\macro_inst|apb_prdata~9_combout ;
wire	[7:0] \macro_inst|apb_pwdata_r ;
//wire	\macro_inst|apb_pwdata_r [0];
wire	\macro_inst|apb_pwdata_r[0]__feeder__LutOut ;
//wire	\macro_inst|apb_pwdata_r [1];
wire	\macro_inst|apb_pwdata_r[1]__feeder__LutOut ;
//wire	\macro_inst|apb_pwdata_r [2];
//wire	\macro_inst|apb_pwdata_r [3];
wire	\macro_inst|apb_pwdata_r[3]__feeder__LutOut ;
//wire	\macro_inst|apb_pwdata_r [4];
wire	\macro_inst|apb_pwdata_r[4]__feeder__LutOut ;
//wire	\macro_inst|apb_pwdata_r [5];
//wire	\macro_inst|apb_pwdata_r [6];
wire	\macro_inst|apb_pwdata_r[6]__feeder__LutOut ;
//wire	\macro_inst|apb_pwdata_r [7];
wire	[0:0] \macro_inst|csen ;
//wire	\macro_inst|csen [0];
wire	\macro_inst|csen[0]~0_combout ;
wire	\macro_inst|ren~0_combout ;
wire	[7:0] \macro_inst|rx_fifo_data ;
//wire	\macro_inst|rx_fifo_data [0];
wire	\macro_inst|rx_fifo_data[0]~feeder_combout ;
//wire	\macro_inst|rx_fifo_data [1];
wire	\macro_inst|rx_fifo_data[1]~feeder_combout ;
//wire	\macro_inst|rx_fifo_data [2];
//wire	\macro_inst|rx_fifo_data [3];
//wire	\macro_inst|rx_fifo_data [4];
wire	\macro_inst|rx_fifo_data[4]~feeder_combout ;
//wire	\macro_inst|rx_fifo_data [5];
wire	\macro_inst|rx_fifo_data[5]~feeder_combout ;
//wire	\macro_inst|rx_fifo_data [6];
wire	\macro_inst|rx_fifo_data[6]~feeder_combout ;
//wire	\macro_inst|rx_fifo_data [7];
wire	\macro_inst|rx_fifo_data[7]~feeder_combout ;
wire	[7:0] \macro_inst|rx_fifo_data_r ;
//wire	\macro_inst|rx_fifo_data_r [0];
wire	\macro_inst|rx_fifo_data_r[0]~feeder_combout ;
//wire	\macro_inst|rx_fifo_data_r [1];
wire	\macro_inst|rx_fifo_data_r[1]~feeder_combout ;
//wire	\macro_inst|rx_fifo_data_r [2];
wire	\macro_inst|rx_fifo_data_r[2]~feeder_combout ;
//wire	\macro_inst|rx_fifo_data_r [3];
wire	\macro_inst|rx_fifo_data_r[3]~feeder_combout ;
//wire	\macro_inst|rx_fifo_data_r [4];
//wire	\macro_inst|rx_fifo_data_r [5];
//wire	\macro_inst|rx_fifo_data_r [6];
wire	\macro_inst|rx_fifo_data_r[6]~feeder_combout ;
//wire	\macro_inst|rx_fifo_data_r [7];
wire	\macro_inst|rx_fifo_data_r[7]~feeder_combout ;
wire	[7:0] \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|q_b ;
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|q_b [0];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|q_b [1];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|q_b [2];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|q_b [3];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|q_b [4];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|q_b [5];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|q_b [6];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|q_b [7];
wire	[17:0] \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB ;
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [9];
wire	[8:0] \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0_PORTBDATAOUT_bus ;
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0_PORTBDATAOUT_bus [0];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [10];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0_PORTBDATAOUT_bus [1];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [11];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0_PORTBDATAOUT_bus [2];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [12];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0_PORTBDATAOUT_bus [3];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [13];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0_PORTBDATAOUT_bus [4];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [14];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0_PORTBDATAOUT_bus [5];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [15];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0_PORTBDATAOUT_bus [6];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [16];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0_PORTBDATAOUT_bus [7];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [7];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0_PORTBDATAOUT_bus [8];
wire	[17:0] \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA ;
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [0];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [10];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [11];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [12];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [13];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [14];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [15];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [16];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [17];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [1];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [2];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [3];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [4];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [5];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [6];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [7];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [8];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [9];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [0];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [17];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [1];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [2];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [3];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [4];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [5];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [6];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [8];
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~10_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~11_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~12_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~13_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~14_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~3_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~4_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~5_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~6_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~7_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~8_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~9_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff~q ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|full_dff~q ;
wire	[9:0] \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa ;
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [0];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [1];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [2];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [3];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [4];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [5];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [6];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [7];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [8];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [9];
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[0]~0_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[1]~1_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[2]~2_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[3]~3_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[4]~4_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[5]~5_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[6]~6_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[7]~7_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[8]~8_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[9]~9_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_lsb~0_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_lsb~q ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita0~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita0~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita1~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita1~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita2~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita2~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita3~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita3~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita4~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita4~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita5~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita5~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita6~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita6~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita7~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita7~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita8~combout ;
wire	[8:0] \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit ;
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [0];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [1];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [2];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [3];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [4];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [5];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [6];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [7];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [8];
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita0~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita0~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita1~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita1~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita2~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita2~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita3~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita3~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita4~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita4~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita5~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita5~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita6~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita6~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita7~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita7~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita8~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita8~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita9~combout ;
wire	[9:0] \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit ;
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [0];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [1];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [2];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [3];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [4];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [5];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [6];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [7];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [8];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [9];
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_0_dff~q ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_1_dff~q ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_2_dff~q ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_1~0_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_1~1_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_2~0_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_2~1_combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout ;
wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout ;
wire	[9:0] \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit ;
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8];
//wire	\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9];
wire	[0:0] \macro_inst|rx_fifo_req ;
//wire	\macro_inst|rx_fifo_req [0];
wire	[0:0] \macro_inst|rx_fifo_wen ;
//wire	\macro_inst|rx_fifo_wen [0];
wire	[0:0] \macro_inst|rx_fifo_wen_r ;
//wire	\macro_inst|rx_fifo_wen_r [0];
wire	\macro_inst|spi_inst|Add0~0_combout ;
wire	\macro_inst|spi_inst|Add0~1 ;
wire	\macro_inst|spi_inst|Add0~10 ;
wire	\macro_inst|spi_inst|Add0~11_combout ;
wire	\macro_inst|spi_inst|Add0~13_combout ;
wire	\macro_inst|spi_inst|Add0~14_combout ;
wire	\macro_inst|spi_inst|Add0~2_combout ;
wire	\macro_inst|spi_inst|Add0~3_combout ;
wire	\macro_inst|spi_inst|Add0~4 ;
wire	\macro_inst|spi_inst|Add0~5_combout ;
wire	\macro_inst|spi_inst|Add0~6_combout ;
wire	\macro_inst|spi_inst|Add0~7 ;
wire	\macro_inst|spi_inst|Add0~8_combout ;
wire	\macro_inst|spi_inst|Add0~9_combout ;
wire	\macro_inst|spi_inst|Equal0~0_combout ;
wire	\macro_inst|spi_inst|always1~0_combout ;
wire	\macro_inst|spi_inst|always7~0_combout ;
wire	\macro_inst|spi_inst|always9~0_combout ;
wire	[0:0] \macro_inst|spi_inst|csen_r ;
//wire	\macro_inst|spi_inst|csen_r [0];
wire	[7:0] \macro_inst|spi_inst|rx_data ;
//wire	\macro_inst|spi_inst|rx_data [0];
wire	\macro_inst|spi_inst|rx_data[0]~feeder_combout ;
//wire	\macro_inst|spi_inst|rx_data [1];
//wire	\macro_inst|spi_inst|rx_data [2];
wire	\macro_inst|spi_inst|rx_data[2]~feeder_combout ;
//wire	\macro_inst|spi_inst|rx_data [3];
//wire	\macro_inst|spi_inst|rx_data [4];
//wire	\macro_inst|spi_inst|rx_data [5];
wire	\macro_inst|spi_inst|rx_data[5]~feeder_combout ;
//wire	\macro_inst|spi_inst|rx_data [6];
wire	\macro_inst|spi_inst|rx_data[6]~feeder_combout ;
//wire	\macro_inst|spi_inst|rx_data [7];
wire	\macro_inst|spi_inst|rx_data[7]~feeder_combout ;
wire	[7:0] \macro_inst|spi_inst|rx_data_r ;
//wire	\macro_inst|spi_inst|rx_data_r [0];
//wire	\macro_inst|spi_inst|rx_data_r [1];
wire	\macro_inst|spi_inst|rx_data_r[1]~feeder_combout ;
//wire	\macro_inst|spi_inst|rx_data_r [2];
//wire	\macro_inst|spi_inst|rx_data_r [3];
wire	\macro_inst|spi_inst|rx_data_r[3]~feeder_combout ;
//wire	\macro_inst|spi_inst|rx_data_r [4];
//wire	\macro_inst|spi_inst|rx_data_r [5];
wire	\macro_inst|spi_inst|rx_data_r[5]~feeder_combout ;
//wire	\macro_inst|spi_inst|rx_data_r [6];
wire	\macro_inst|spi_inst|rx_data_r[6]~feeder_combout ;
//wire	\macro_inst|spi_inst|rx_data_r [7];
wire	\macro_inst|spi_inst|rx_data_r[7]~feeder_combout ;
wire	\macro_inst|spi_inst|rx_en~q ;
wire	[4:0] \macro_inst|spi_inst|sck_cnt ;
//wire	\macro_inst|spi_inst|sck_cnt [0];
wire	\macro_inst|spi_inst|sck_cnt[0]~0_combout ;
//wire	\macro_inst|spi_inst|sck_cnt [1];
//wire	\macro_inst|spi_inst|sck_cnt [2];
//wire	\macro_inst|spi_inst|sck_cnt [3];
//wire	\macro_inst|spi_inst|sck_cnt [4];
wire	[0:0] \macro_inst|spi_inst|sck_cnt_bit0 ;
//wire	\macro_inst|spi_inst|sck_cnt_bit0 [0];
wire	\macro_inst|spi_inst|sck_cnt_bit0[0]~feeder_combout ;
wire	\macro_inst|spi_inst|sck_cnt_bit0~0_combout ;
wire	\macro_inst|spi_inst|sck_cnt_bit0~1_combout ;
wire	[0:0] \macro_inst|spi_inst|sck_r ;
//wire	\macro_inst|spi_inst|sck_r [0];
wire	\macro_inst|spi_inst|sck~q ;
wire	\macro_inst|spi_inst|scs~0_combout ;
wire	\macro_inst|spi_inst|scs~1_combout ;
wire	\macro_inst|spi_inst|scs~q ;
wire	[7:0] \macro_inst|spi_inst|tx_data_r ;
//wire	\macro_inst|spi_inst|tx_data_r [0];
//wire	\macro_inst|spi_inst|tx_data_r [1];
//wire	\macro_inst|spi_inst|tx_data_r [2];
wire	\macro_inst|spi_inst|tx_data_r[2]~feeder_combout ;
//wire	\macro_inst|spi_inst|tx_data_r [3];
//wire	\macro_inst|spi_inst|tx_data_r [4];
wire	\macro_inst|spi_inst|tx_data_r[4]~feeder_combout ;
//wire	\macro_inst|spi_inst|tx_data_r [5];
wire	\macro_inst|spi_inst|tx_data_r[5]~feeder_combout ;
//wire	\macro_inst|spi_inst|tx_data_r [6];
//wire	\macro_inst|spi_inst|tx_data_r [7];
wire	\macro_inst|spi_inst|tx_data_r[7]~1_combout ;
wire	\macro_inst|spi_inst|tx_data_r~0_combout ;
wire	\macro_inst|spi_inst|tx_data_r~2_combout ;
wire	\macro_inst|spi_inst|tx_data_r~3_combout ;
wire	\macro_inst|spi_inst|tx_data_r~4_combout ;
wire	\macro_inst|spi_inst|tx_data_r~5_combout ;
wire	\macro_inst|spi_inst|tx_data_r~6_combout ;
wire	\macro_inst|spi_inst|tx_data_r~7_combout ;
wire	\macro_inst|spi_inst|tx_data_r~8_combout ;
wire	\macro_inst|spi_inst|tx_data_r~9_combout ;
wire	[7:0] \macro_inst|spi_inst|tx_en_r ;
//wire	\macro_inst|spi_inst|tx_en_r [0];
//wire	\macro_inst|spi_inst|tx_en_r [1];
//wire	\macro_inst|spi_inst|tx_en_r [2];
//wire	\macro_inst|spi_inst|tx_en_r [3];
wire	\macro_inst|spi_inst|tx_en_r[3]~feeder_combout ;
//wire	\macro_inst|spi_inst|tx_en_r [4];
wire	\macro_inst|spi_inst|tx_en_r[4]~feeder_combout ;
//wire	\macro_inst|spi_inst|tx_en_r [5];
//wire	\macro_inst|spi_inst|tx_en_r [6];
//wire	\macro_inst|spi_inst|tx_en_r [7];
wire	\macro_inst|spi_inst|tx_req~q ;
wire	[7:0] \macro_inst|tx_data ;
//wire	\macro_inst|tx_data [0];
//wire	\macro_inst|tx_data [1];
//wire	\macro_inst|tx_data [2];
//wire	\macro_inst|tx_data [3];
//wire	\macro_inst|tx_data [4];
//wire	\macro_inst|tx_data [5];
//wire	\macro_inst|tx_data [6];
//wire	\macro_inst|tx_data [7];
wire	[0:0] \macro_inst|tx_en ;
//wire	\macro_inst|tx_en [0];
wire	[2:0] \macro_inst|tx_fifo_empty_r ;
//wire	\macro_inst|tx_fifo_empty_r [0];
wire	\macro_inst|tx_fifo_empty_r[0]~0_combout ;
//wire	\macro_inst|tx_fifo_empty_r [1];
//wire	\macro_inst|tx_fifo_empty_r [2];
wire	[17:0] \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB ;
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [9];
wire	[8:0] \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus ;
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [0];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [10];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [1];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [11];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [2];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [12];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [3];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [13];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [4];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [14];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [5];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [15];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [6];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [16];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [7];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [7];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [8];
wire	[17:0] \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA ;
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [0];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [10];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [11];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [12];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [13];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [14];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [15];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [16];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [17];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [1];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [2];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [3];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [4];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [5];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [6];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [7];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [8];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [9];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [0];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [17];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [1];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [2];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [3];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [4];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [5];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [6];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [8];
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4_combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~3_combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~4_combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~combout ;
wire	[9:0] \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit ;
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9];
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~combout ;
wire	[9:0] \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit ;
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9];
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout ;
wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout ;
wire	[9:0] \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit ;
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8];
//wire	\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9];
wire	[0:0] \macro_inst|tx_fifo_rdreq ;
//wire	\macro_inst|tx_fifo_rdreq [0];
wire	[0:0] \macro_inst|tx_fifo_rdreq_r ;
//wire	\macro_inst|tx_fifo_rdreq_r [0];
wire	[0:0] \macro_inst|tx_fifo_wreq ;
//wire	\macro_inst|tx_fifo_wreq [0];
wire	[31:0] mem_ahb_haddr;
//wire	mem_ahb_haddr[0];
//wire	mem_ahb_haddr[10];
//wire	mem_ahb_haddr[11];
//wire	mem_ahb_haddr[12];
//wire	mem_ahb_haddr[13];
//wire	mem_ahb_haddr[14];
//wire	mem_ahb_haddr[15];
//wire	mem_ahb_haddr[16];
//wire	mem_ahb_haddr[17];
//wire	mem_ahb_haddr[18];
//wire	mem_ahb_haddr[19];
//wire	mem_ahb_haddr[1];
//wire	mem_ahb_haddr[20];
//wire	mem_ahb_haddr[21];
//wire	mem_ahb_haddr[22];
//wire	mem_ahb_haddr[23];
//wire	mem_ahb_haddr[24];
//wire	mem_ahb_haddr[25];
//wire	mem_ahb_haddr[26];
//wire	mem_ahb_haddr[27];
//wire	mem_ahb_haddr[28];
//wire	mem_ahb_haddr[29];
//wire	mem_ahb_haddr[2];
//wire	mem_ahb_haddr[30];
//wire	mem_ahb_haddr[31];
//wire	mem_ahb_haddr[3];
//wire	mem_ahb_haddr[4];
//wire	mem_ahb_haddr[5];
//wire	mem_ahb_haddr[6];
//wire	mem_ahb_haddr[7];
//wire	mem_ahb_haddr[8];
//wire	mem_ahb_haddr[9];
wire	[31:0] mem_ahb_hrdata;
//wire	mem_ahb_hrdata[0];
//wire	mem_ahb_hrdata[10];
//wire	mem_ahb_hrdata[11];
//wire	mem_ahb_hrdata[12];
//wire	mem_ahb_hrdata[13];
//wire	mem_ahb_hrdata[14];
//wire	mem_ahb_hrdata[15];
//wire	mem_ahb_hrdata[16];
//wire	mem_ahb_hrdata[17];
//wire	mem_ahb_hrdata[18];
//wire	mem_ahb_hrdata[19];
//wire	mem_ahb_hrdata[1];
//wire	mem_ahb_hrdata[20];
//wire	mem_ahb_hrdata[21];
//wire	mem_ahb_hrdata[22];
//wire	mem_ahb_hrdata[23];
//wire	mem_ahb_hrdata[24];
//wire	mem_ahb_hrdata[25];
//wire	mem_ahb_hrdata[26];
//wire	mem_ahb_hrdata[27];
//wire	mem_ahb_hrdata[28];
//wire	mem_ahb_hrdata[29];
//wire	mem_ahb_hrdata[2];
//wire	mem_ahb_hrdata[30];
//wire	mem_ahb_hrdata[31];
//wire	mem_ahb_hrdata[3];
//wire	mem_ahb_hrdata[4];
//wire	mem_ahb_hrdata[5];
//wire	mem_ahb_hrdata[6];
//wire	mem_ahb_hrdata[7];
//wire	mem_ahb_hrdata[8];
//wire	mem_ahb_hrdata[9];
wire	\mem_ahb_hresp~combout ;
wire	[1:0] mem_ahb_htrans;
//wire	mem_ahb_htrans[0];
//wire	mem_ahb_htrans[1];
wire	[31:0] mem_ahb_hwdata;
//wire	mem_ahb_hwdata[0];
//wire	mem_ahb_hwdata[10];
//wire	mem_ahb_hwdata[11];
//wire	mem_ahb_hwdata[12];
//wire	mem_ahb_hwdata[13];
//wire	mem_ahb_hwdata[14];
//wire	mem_ahb_hwdata[15];
//wire	mem_ahb_hwdata[16];
//wire	mem_ahb_hwdata[17];
//wire	mem_ahb_hwdata[18];
//wire	mem_ahb_hwdata[19];
//wire	mem_ahb_hwdata[1];
//wire	mem_ahb_hwdata[20];
//wire	mem_ahb_hwdata[21];
//wire	mem_ahb_hwdata[22];
//wire	mem_ahb_hwdata[23];
//wire	mem_ahb_hwdata[24];
//wire	mem_ahb_hwdata[25];
//wire	mem_ahb_hwdata[26];
//wire	mem_ahb_hwdata[27];
//wire	mem_ahb_hwdata[28];
//wire	mem_ahb_hwdata[29];
//wire	mem_ahb_hwdata[2];
//wire	mem_ahb_hwdata[30];
//wire	mem_ahb_hwdata[31];
//wire	mem_ahb_hwdata[3];
//wire	mem_ahb_hwdata[4];
//wire	mem_ahb_hwdata[5];
//wire	mem_ahb_hwdata[6];
//wire	mem_ahb_hwdata[7];
//wire	mem_ahb_hwdata[8];
//wire	mem_ahb_hwdata[9];
wire	[4:0] \pll_inst|auto_generated|clk ;
//wire	\pll_inst|auto_generated|clk [0];
//wire	\pll_inst|auto_generated|clk [1];
//wire	\pll_inst|auto_generated|clk [2];
//wire	\pll_inst|auto_generated|clk [3];
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X49_Y2_SIG_VCC ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X50_Y2_SIG_VCC ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y1_SIG_VCC ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y2_SIG_VCC ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X53_Y1_SIG_VCC ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X54_Y1_SIG_VCC ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X54_Y2_SIG_VCC ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X56_Y1_SIG_VCC ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X57_Y2_SIG_VCC ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X58_Y2_SIG_VCC ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X59_Y2_SIG_VCC ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ahb2apb_inst|comb~0_combout_X53_Y2_SIG_SIG ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y2_SIG_SIG ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ahb2apb_inst|pwrite~0_combout_X51_Y2_SIG_SIG ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ren~0_combout_X53_Y2_SIG_SIG ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ren~0_combout_X56_Y2_SIG_SIG ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2_combout_X57_Y2_SIG_SIG ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~9_combout_X59_Y2_SIG_SIG ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout_X58_Y2_SIG_SIG ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y2_SIG_SIG ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always7~0_combout_X51_Y1_SIG_SIG ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always9~0_combout_X51_Y1_SIG_SIG ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|sck_cnt[0]~0_combout_X50_Y2_SIG_SIG ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|tx_data_r[7]~1_combout_X53_Y1_SIG_SIG ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout_X49_Y2_SIG_SIG ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout_X56_Y1_SIG_SIG ;
wire	\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y1_SIG_SIG ;
//wire	\pll_inst|auto_generated|clk [4];
wire	[4:0] \pll_inst|auto_generated|pll1_CLK_bus ;
//wire	\pll_inst|auto_generated|pll1_CLK_bus [0];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [1];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [2];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [3];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [4];
wire	\pll_inst|auto_generated|pll1~FBOUT ;
wire	\pll_inst|auto_generated|pll_lock_sync~feeder_combout ;
wire	\pll_inst|auto_generated|pll_lock_sync~q ;
wire	\rv32.dmactive ;
wire	\rv32.ext_dma_DMACCLR[0] ;
wire	\rv32.ext_dma_DMACCLR[1] ;
wire	\rv32.ext_dma_DMACCLR[2] ;
wire	\rv32.ext_dma_DMACCLR[3] ;
wire	\rv32.ext_dma_DMACTC[0] ;
wire	\rv32.ext_dma_DMACTC[1] ;
wire	\rv32.ext_dma_DMACTC[2] ;
wire	\rv32.ext_dma_DMACTC[3] ;
wire	\rv32.gpio0_io_out_data[0] ;
wire	\rv32.gpio0_io_out_data[1] ;
wire	\rv32.gpio0_io_out_data[2] ;
wire	\rv32.gpio0_io_out_data[3] ;
wire	\rv32.gpio0_io_out_data[4] ;
wire	\rv32.gpio0_io_out_data[5] ;
wire	\rv32.gpio0_io_out_data[6] ;
wire	\rv32.gpio0_io_out_data[7] ;
wire	\rv32.gpio0_io_out_en[0] ;
wire	\rv32.gpio0_io_out_en[1] ;
wire	\rv32.gpio0_io_out_en[2] ;
wire	\rv32.gpio0_io_out_en[3] ;
wire	\rv32.gpio0_io_out_en[4] ;
wire	\rv32.gpio0_io_out_en[5] ;
wire	\rv32.gpio0_io_out_en[6] ;
wire	\rv32.gpio0_io_out_en[7] ;
wire	\rv32.gpio1_io_out_data[0] ;
wire	\rv32.gpio1_io_out_data[1] ;
wire	\rv32.gpio1_io_out_data[2] ;
wire	\rv32.gpio1_io_out_data[3] ;
wire	\rv32.gpio1_io_out_data[4] ;
wire	\rv32.gpio1_io_out_data[5] ;
wire	\rv32.gpio1_io_out_data[6] ;
wire	\rv32.gpio1_io_out_data[7] ;
wire	\rv32.gpio1_io_out_en[0] ;
wire	\rv32.gpio1_io_out_en[1] ;
wire	\rv32.gpio1_io_out_en[2] ;
wire	\rv32.gpio1_io_out_en[3] ;
wire	\rv32.gpio1_io_out_en[4] ;
wire	\rv32.gpio1_io_out_en[5] ;
wire	\rv32.gpio1_io_out_en[6] ;
wire	\rv32.gpio1_io_out_en[7] ;
wire	\rv32.gpio2_io_out_data[0] ;
wire	\rv32.gpio2_io_out_data[1] ;
wire	\rv32.gpio2_io_out_data[2] ;
wire	\rv32.gpio2_io_out_data[3] ;
wire	\rv32.gpio2_io_out_data[4] ;
wire	\rv32.gpio2_io_out_data[5] ;
wire	\rv32.gpio2_io_out_data[6] ;
wire	\rv32.gpio2_io_out_data[7] ;
wire	\rv32.gpio2_io_out_en[0] ;
wire	\rv32.gpio2_io_out_en[1] ;
wire	\rv32.gpio2_io_out_en[2] ;
wire	\rv32.gpio2_io_out_en[3] ;
wire	\rv32.gpio2_io_out_en[4] ;
wire	\rv32.gpio2_io_out_en[5] ;
wire	\rv32.gpio2_io_out_en[6] ;
wire	\rv32.gpio2_io_out_en[7] ;
wire	\rv32.gpio3_io_out_data[0] ;
wire	\rv32.gpio3_io_out_data[1] ;
wire	\rv32.gpio3_io_out_data[2] ;
wire	\rv32.gpio3_io_out_data[3] ;
wire	\rv32.gpio3_io_out_data[4] ;
wire	\rv32.gpio3_io_out_data[5] ;
wire	\rv32.gpio3_io_out_data[6] ;
wire	\rv32.gpio3_io_out_data[7] ;
wire	\rv32.gpio3_io_out_en[0] ;
wire	\rv32.gpio3_io_out_en[1] ;
wire	\rv32.gpio3_io_out_en[2] ;
wire	\rv32.gpio3_io_out_en[3] ;
wire	\rv32.gpio3_io_out_en[4] ;
wire	\rv32.gpio3_io_out_en[5] ;
wire	\rv32.gpio3_io_out_en[6] ;
wire	\rv32.gpio3_io_out_en[7] ;
wire	\rv32.gpio4_io_out_data[0] ;
wire	\rv32.gpio4_io_out_data[1] ;
wire	\rv32.gpio4_io_out_data[2] ;
wire	\rv32.gpio4_io_out_data[3] ;
wire	\rv32.gpio4_io_out_data[4] ;
wire	\rv32.gpio4_io_out_data[5] ;
wire	\rv32.gpio4_io_out_data[6] ;
wire	\rv32.gpio4_io_out_data[7] ;
wire	\rv32.gpio4_io_out_en[0] ;
wire	\rv32.gpio4_io_out_en[1] ;
wire	\rv32.gpio4_io_out_en[2] ;
wire	\rv32.gpio4_io_out_en[3] ;
wire	\rv32.gpio4_io_out_en[4] ;
wire	\rv32.gpio4_io_out_en[5] ;
wire	\rv32.gpio4_io_out_en[6] ;
wire	\rv32.gpio4_io_out_en[7] ;
wire	\rv32.gpio5_io_out_data[0] ;
wire	\rv32.gpio5_io_out_data[1] ;
wire	\rv32.gpio5_io_out_data[2] ;
wire	\rv32.gpio5_io_out_data[3] ;
wire	\rv32.gpio5_io_out_data[4] ;
wire	\rv32.gpio5_io_out_data[5] ;
wire	\rv32.gpio5_io_out_data[6] ;
wire	\rv32.gpio5_io_out_data[7] ;
wire	\rv32.gpio5_io_out_en[0] ;
wire	\rv32.gpio5_io_out_en[1] ;
wire	\rv32.gpio5_io_out_en[2] ;
wire	\rv32.gpio5_io_out_en[3] ;
wire	\rv32.gpio5_io_out_en[4] ;
wire	\rv32.gpio5_io_out_en[5] ;
wire	\rv32.gpio5_io_out_en[6] ;
wire	\rv32.gpio5_io_out_en[7] ;
wire	\rv32.gpio6_io_out_data[0] ;
wire	\rv32.gpio6_io_out_data[1] ;
wire	\rv32.gpio6_io_out_data[2] ;
wire	\rv32.gpio6_io_out_data[3] ;
wire	\rv32.gpio6_io_out_data[4] ;
wire	\rv32.gpio6_io_out_data[5] ;
wire	\rv32.gpio6_io_out_data[6] ;
wire	\rv32.gpio6_io_out_data[7] ;
wire	\rv32.gpio6_io_out_en[0] ;
wire	\rv32.gpio6_io_out_en[1] ;
wire	\rv32.gpio6_io_out_en[2] ;
wire	\rv32.gpio6_io_out_en[3] ;
wire	\rv32.gpio6_io_out_en[4] ;
wire	\rv32.gpio6_io_out_en[5] ;
wire	\rv32.gpio6_io_out_en[6] ;
wire	\rv32.gpio6_io_out_en[7] ;
wire	\rv32.gpio7_io_out_data[0] ;
wire	\rv32.gpio7_io_out_data[1] ;
wire	\rv32.gpio7_io_out_data[2] ;
wire	\rv32.gpio7_io_out_data[3] ;
wire	\rv32.gpio7_io_out_data[4] ;
wire	\rv32.gpio7_io_out_data[5] ;
wire	\rv32.gpio7_io_out_data[6] ;
wire	\rv32.gpio7_io_out_data[7] ;
wire	\rv32.gpio7_io_out_en[0] ;
wire	\rv32.gpio7_io_out_en[1] ;
wire	\rv32.gpio7_io_out_en[2] ;
wire	\rv32.gpio7_io_out_en[3] ;
wire	\rv32.gpio7_io_out_en[4] ;
wire	\rv32.gpio7_io_out_en[5] ;
wire	\rv32.gpio7_io_out_en[6] ;
wire	\rv32.gpio7_io_out_en[7] ;
wire	\rv32.gpio8_io_out_data[0] ;
wire	\rv32.gpio8_io_out_data[1] ;
wire	\rv32.gpio8_io_out_data[2] ;
wire	\rv32.gpio8_io_out_data[3] ;
wire	\rv32.gpio8_io_out_data[4] ;
wire	\rv32.gpio8_io_out_data[5] ;
wire	\rv32.gpio8_io_out_data[6] ;
wire	\rv32.gpio8_io_out_data[7] ;
wire	\rv32.gpio8_io_out_en[0] ;
wire	\rv32.gpio8_io_out_en[1] ;
wire	\rv32.gpio8_io_out_en[2] ;
wire	\rv32.gpio8_io_out_en[3] ;
wire	\rv32.gpio8_io_out_en[4] ;
wire	\rv32.gpio8_io_out_en[5] ;
wire	\rv32.gpio8_io_out_en[6] ;
wire	\rv32.gpio8_io_out_en[7] ;
wire	\rv32.gpio9_io_out_data[0] ;
wire	\rv32.gpio9_io_out_data[1] ;
wire	\rv32.gpio9_io_out_data[2] ;
wire	\rv32.gpio9_io_out_data[3] ;
wire	\rv32.gpio9_io_out_data[4] ;
wire	\rv32.gpio9_io_out_data[5] ;
wire	\rv32.gpio9_io_out_data[6] ;
wire	\rv32.gpio9_io_out_data[7] ;
wire	\rv32.gpio9_io_out_en[0] ;
wire	\rv32.gpio9_io_out_en[1] ;
wire	\rv32.gpio9_io_out_en[2] ;
wire	\rv32.gpio9_io_out_en[3] ;
wire	\rv32.gpio9_io_out_en[4] ;
wire	\rv32.gpio9_io_out_en[5] ;
wire	\rv32.gpio9_io_out_en[6] ;
wire	\rv32.gpio9_io_out_en[7] ;
wire	\rv32.mem_ahb_haddr[0] ;
wire	\rv32.mem_ahb_haddr[10] ;
wire	\rv32.mem_ahb_haddr[11] ;
wire	\rv32.mem_ahb_haddr[12] ;
wire	\rv32.mem_ahb_haddr[13] ;
wire	\rv32.mem_ahb_haddr[14] ;
wire	\rv32.mem_ahb_haddr[15] ;
wire	\rv32.mem_ahb_haddr[16] ;
wire	\rv32.mem_ahb_haddr[17] ;
wire	\rv32.mem_ahb_haddr[18] ;
wire	\rv32.mem_ahb_haddr[19] ;
wire	\rv32.mem_ahb_haddr[1] ;
wire	\rv32.mem_ahb_haddr[20] ;
wire	\rv32.mem_ahb_haddr[21] ;
wire	\rv32.mem_ahb_haddr[22] ;
wire	\rv32.mem_ahb_haddr[23] ;
wire	\rv32.mem_ahb_haddr[24] ;
wire	\rv32.mem_ahb_haddr[25] ;
wire	\rv32.mem_ahb_haddr[26] ;
wire	\rv32.mem_ahb_haddr[27] ;
wire	\rv32.mem_ahb_haddr[28] ;
wire	\rv32.mem_ahb_haddr[29] ;
wire	\rv32.mem_ahb_haddr[2] ;
wire	\rv32.mem_ahb_haddr[30] ;
wire	\rv32.mem_ahb_haddr[31] ;
wire	\rv32.mem_ahb_haddr[3] ;
wire	\rv32.mem_ahb_haddr[4] ;
wire	\rv32.mem_ahb_haddr[5] ;
wire	\rv32.mem_ahb_haddr[6] ;
wire	\rv32.mem_ahb_haddr[7] ;
wire	\rv32.mem_ahb_haddr[8] ;
wire	\rv32.mem_ahb_haddr[9] ;
wire	\rv32.mem_ahb_hburst[0] ;
wire	\rv32.mem_ahb_hburst[1] ;
wire	\rv32.mem_ahb_hburst[2] ;
wire	\rv32.mem_ahb_hready ;
wire	\rv32.mem_ahb_hsize[0] ;
wire	\rv32.mem_ahb_hsize[1] ;
wire	\rv32.mem_ahb_hsize[2] ;
wire	\rv32.mem_ahb_htrans[0] ;
wire	\rv32.mem_ahb_htrans[1] ;
wire	\rv32.mem_ahb_hwdata[0] ;
wire	\rv32.mem_ahb_hwdata[10] ;
wire	\rv32.mem_ahb_hwdata[11] ;
wire	\rv32.mem_ahb_hwdata[12] ;
wire	\rv32.mem_ahb_hwdata[13] ;
wire	\rv32.mem_ahb_hwdata[14] ;
wire	\rv32.mem_ahb_hwdata[15] ;
wire	\rv32.mem_ahb_hwdata[16] ;
wire	\rv32.mem_ahb_hwdata[17] ;
wire	\rv32.mem_ahb_hwdata[18] ;
wire	\rv32.mem_ahb_hwdata[19] ;
wire	\rv32.mem_ahb_hwdata[1] ;
wire	\rv32.mem_ahb_hwdata[20] ;
wire	\rv32.mem_ahb_hwdata[21] ;
wire	\rv32.mem_ahb_hwdata[22] ;
wire	\rv32.mem_ahb_hwdata[23] ;
wire	\rv32.mem_ahb_hwdata[24] ;
wire	\rv32.mem_ahb_hwdata[25] ;
wire	\rv32.mem_ahb_hwdata[26] ;
wire	\rv32.mem_ahb_hwdata[27] ;
wire	\rv32.mem_ahb_hwdata[28] ;
wire	\rv32.mem_ahb_hwdata[29] ;
wire	\rv32.mem_ahb_hwdata[2] ;
wire	\rv32.mem_ahb_hwdata[30] ;
wire	\rv32.mem_ahb_hwdata[31] ;
wire	\rv32.mem_ahb_hwdata[3] ;
wire	\rv32.mem_ahb_hwdata[4] ;
wire	\rv32.mem_ahb_hwdata[5] ;
wire	\rv32.mem_ahb_hwdata[6] ;
wire	\rv32.mem_ahb_hwdata[7] ;
wire	\rv32.mem_ahb_hwdata[8] ;
wire	\rv32.mem_ahb_hwdata[9] ;
wire	\rv32.mem_ahb_hwrite ;
wire	\rv32.resetn_out ;
wire	\rv32.slave_ahb_hrdata[0] ;
wire	\rv32.slave_ahb_hrdata[10] ;
wire	\rv32.slave_ahb_hrdata[11] ;
wire	\rv32.slave_ahb_hrdata[12] ;
wire	\rv32.slave_ahb_hrdata[13] ;
wire	\rv32.slave_ahb_hrdata[14] ;
wire	\rv32.slave_ahb_hrdata[15] ;
wire	\rv32.slave_ahb_hrdata[16] ;
wire	\rv32.slave_ahb_hrdata[17] ;
wire	\rv32.slave_ahb_hrdata[18] ;
wire	\rv32.slave_ahb_hrdata[19] ;
wire	\rv32.slave_ahb_hrdata[1] ;
wire	\rv32.slave_ahb_hrdata[20] ;
wire	\rv32.slave_ahb_hrdata[21] ;
wire	\rv32.slave_ahb_hrdata[22] ;
wire	\rv32.slave_ahb_hrdata[23] ;
wire	\rv32.slave_ahb_hrdata[24] ;
wire	\rv32.slave_ahb_hrdata[25] ;
wire	\rv32.slave_ahb_hrdata[26] ;
wire	\rv32.slave_ahb_hrdata[27] ;
wire	\rv32.slave_ahb_hrdata[28] ;
wire	\rv32.slave_ahb_hrdata[29] ;
wire	\rv32.slave_ahb_hrdata[2] ;
wire	\rv32.slave_ahb_hrdata[30] ;
wire	\rv32.slave_ahb_hrdata[31] ;
wire	\rv32.slave_ahb_hrdata[3] ;
wire	\rv32.slave_ahb_hrdata[4] ;
wire	\rv32.slave_ahb_hrdata[5] ;
wire	\rv32.slave_ahb_hrdata[6] ;
wire	\rv32.slave_ahb_hrdata[7] ;
wire	\rv32.slave_ahb_hrdata[8] ;
wire	\rv32.slave_ahb_hrdata[9] ;
wire	\rv32.slave_ahb_hreadyout ;
wire	\rv32.slave_ahb_hresp ;
wire	\rv32.swj_JTAGIR[0] ;
wire	\rv32.swj_JTAGIR[1] ;
wire	\rv32.swj_JTAGIR[2] ;
wire	\rv32.swj_JTAGIR[3] ;
wire	\rv32.swj_JTAGNSW ;
wire	\rv32.swj_JTAGSTATE[0] ;
wire	\rv32.swj_JTAGSTATE[1] ;
wire	\rv32.swj_JTAGSTATE[2] ;
wire	\rv32.swj_JTAGSTATE[3] ;
wire	\rv32.sys_ctrl_clkSource[0] ;
wire	\rv32.sys_ctrl_clkSource[1] ;
wire	\rv32.sys_ctrl_hseBypass ;
wire	\rv32.sys_ctrl_hseEnable ;
wire	\rv32.sys_ctrl_pllEnable ;
wire	\rv32.sys_ctrl_sleep ;
wire	\rv32.sys_ctrl_standby ;
wire	\rv32.sys_ctrl_stop ;
wire	[31:0] slave_ahb_haddr;
//wire	slave_ahb_haddr[0];
//wire	slave_ahb_haddr[10];
//wire	slave_ahb_haddr[11];
//wire	slave_ahb_haddr[12];
//wire	slave_ahb_haddr[13];
//wire	slave_ahb_haddr[14];
//wire	slave_ahb_haddr[15];
//wire	slave_ahb_haddr[16];
//wire	slave_ahb_haddr[17];
//wire	slave_ahb_haddr[18];
//wire	slave_ahb_haddr[19];
//wire	slave_ahb_haddr[1];
//wire	slave_ahb_haddr[20];
//wire	slave_ahb_haddr[21];
//wire	slave_ahb_haddr[22];
//wire	slave_ahb_haddr[23];
//wire	slave_ahb_haddr[24];
//wire	slave_ahb_haddr[25];
//wire	slave_ahb_haddr[26];
//wire	slave_ahb_haddr[27];
//wire	slave_ahb_haddr[28];
//wire	slave_ahb_haddr[29];
//wire	slave_ahb_haddr[2];
//wire	slave_ahb_haddr[30];
//wire	slave_ahb_haddr[31];
//wire	slave_ahb_haddr[3];
//wire	slave_ahb_haddr[4];
//wire	slave_ahb_haddr[5];
//wire	slave_ahb_haddr[6];
//wire	slave_ahb_haddr[7];
//wire	slave_ahb_haddr[8];
//wire	slave_ahb_haddr[9];
wire	[2:0] slave_ahb_hburst;
//wire	slave_ahb_hburst[0];
//wire	slave_ahb_hburst[1];
//wire	slave_ahb_hburst[2];
wire	\slave_ahb_hready~combout ;
wire	\slave_ahb_hsel~combout ;
wire	[2:0] slave_ahb_hsize;
//wire	slave_ahb_hsize[0];
//wire	slave_ahb_hsize[1];
//wire	slave_ahb_hsize[2];
wire	[1:0] slave_ahb_htrans;
//wire	slave_ahb_htrans[0];
//wire	slave_ahb_htrans[1];
wire	[31:0] slave_ahb_hwdata;
//wire	slave_ahb_hwdata[0];
//wire	slave_ahb_hwdata[10];
//wire	slave_ahb_hwdata[11];
//wire	slave_ahb_hwdata[12];
//wire	slave_ahb_hwdata[13];
//wire	slave_ahb_hwdata[14];
//wire	slave_ahb_hwdata[15];
//wire	slave_ahb_hwdata[16];
//wire	slave_ahb_hwdata[17];
//wire	slave_ahb_hwdata[18];
//wire	slave_ahb_hwdata[19];
//wire	slave_ahb_hwdata[1];
//wire	slave_ahb_hwdata[20];
//wire	slave_ahb_hwdata[21];
//wire	slave_ahb_hwdata[22];
//wire	slave_ahb_hwdata[23];
//wire	slave_ahb_hwdata[24];
//wire	slave_ahb_hwdata[25];
//wire	slave_ahb_hwdata[26];
//wire	slave_ahb_hwdata[27];
//wire	slave_ahb_hwdata[28];
//wire	slave_ahb_hwdata[29];
//wire	slave_ahb_hwdata[2];
//wire	slave_ahb_hwdata[30];
//wire	slave_ahb_hwdata[31];
//wire	slave_ahb_hwdata[3];
//wire	slave_ahb_hwdata[4];
//wire	slave_ahb_hwdata[5];
//wire	slave_ahb_hwdata[6];
//wire	slave_ahb_hwdata[7];
//wire	slave_ahb_hwdata[8];
//wire	slave_ahb_hwdata[9];
wire	\slave_ahb_hwrite~combout ;
wire	\sys_resetn~combout ;
wire	\sys_resetn~combout__AsyncReset_X51_Y2_SIG ;
wire	\sys_resetn~combout__AsyncReset_X52_Y2_SIG ;
wire	\sys_resetn~combout__AsyncReset_X53_Y2_SIG ;
wire	\sys_resetn~combout__AsyncReset_X56_Y2_SIG ;
wire	unknown;
wire	\~GND~combout ;
wire	\~VCC~combout ;

wire vcc;
wire gnd;
assign vcc = 1'b1;
assign gnd = 1'b0;

alta_rio \PIN_16~output (
	.padio(PIN_16),
	.datain(\rv32.gpio0_io_out_data[2] ),
	.oe(\rv32.gpio0_io_out_en[2] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_16~input_o ),
	.regout());
defparam \PIN_16~output .coord_x = 20;
defparam \PIN_16~output .coord_y = 13;
defparam \PIN_16~output .coord_z = 3;
defparam \PIN_16~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_16~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_16~output .IN_POWERUP = 1'b0;
defparam \PIN_16~output .OUT_REG_MODE = 1'b0;
defparam \PIN_16~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_16~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_16~output .OUT_POWERUP = 1'b0;
defparam \PIN_16~output .OE_REG_MODE = 1'b0;
defparam \PIN_16~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_16~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_16~output .OE_POWERUP = 1'b0;
defparam \PIN_16~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_16~output .CFG_INPUT_EN = 1'b1;
defparam \PIN_16~output .CFG_PULL_UP = 1'b0;
defparam \PIN_16~output .CFG_SLR = 1'b0;
defparam \PIN_16~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_16~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_16~output .CFG_KEEP = 2'b00;
defparam \PIN_16~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_16~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_16~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_16~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_16~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_16~output .OUT_DELAY = 1'b0;
defparam \PIN_16~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_16~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_23~output (
	.padio(PIN_23),
	.datain(\rv32.gpio0_io_out_data[7] ),
	.oe(\rv32.gpio0_io_out_en[7] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_23~input_o ),
	.regout());
defparam \PIN_23~output .coord_x = 18;
defparam \PIN_23~output .coord_y = 13;
defparam \PIN_23~output .coord_z = 3;
defparam \PIN_23~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_23~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_23~output .IN_POWERUP = 1'b0;
defparam \PIN_23~output .OUT_REG_MODE = 1'b0;
defparam \PIN_23~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_23~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_23~output .OUT_POWERUP = 1'b0;
defparam \PIN_23~output .OE_REG_MODE = 1'b0;
defparam \PIN_23~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_23~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_23~output .OE_POWERUP = 1'b0;
defparam \PIN_23~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_23~output .CFG_INPUT_EN = 1'b1;
defparam \PIN_23~output .CFG_PULL_UP = 1'b0;
defparam \PIN_23~output .CFG_SLR = 1'b0;
defparam \PIN_23~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_23~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_23~output .CFG_KEEP = 2'b00;
defparam \PIN_23~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_23~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_23~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_23~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_23~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_23~output .OUT_DELAY = 1'b0;
defparam \PIN_23~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_23~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_24~output (
	.padio(PIN_24),
	.datain(\rv32.gpio4_io_out_data[7] ),
	.oe(\rv32.gpio4_io_out_en[7] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout());
defparam \PIN_24~output .coord_x = 18;
defparam \PIN_24~output .coord_y = 13;
defparam \PIN_24~output .coord_z = 2;
defparam \PIN_24~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_24~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_24~output .IN_POWERUP = 1'b0;
defparam \PIN_24~output .OUT_REG_MODE = 1'b0;
defparam \PIN_24~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_24~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_24~output .OUT_POWERUP = 1'b0;
defparam \PIN_24~output .OE_REG_MODE = 1'b0;
defparam \PIN_24~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_24~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_24~output .OE_POWERUP = 1'b0;
defparam \PIN_24~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_24~output .CFG_INPUT_EN = 1'b0;
defparam \PIN_24~output .CFG_PULL_UP = 1'b0;
defparam \PIN_24~output .CFG_SLR = 1'b0;
defparam \PIN_24~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_24~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_24~output .CFG_KEEP = 2'b00;
defparam \PIN_24~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_24~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_24~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_24~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_24~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_24~output .OUT_DELAY = 1'b0;
defparam \PIN_24~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_24~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_25~output (
	.padio(PIN_25),
	.datain(\rv32.gpio0_io_out_data[4] ),
	.oe(\rv32.gpio0_io_out_en[4] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_25~input_o ),
	.regout());
defparam \PIN_25~output .coord_x = 18;
defparam \PIN_25~output .coord_y = 13;
defparam \PIN_25~output .coord_z = 1;
defparam \PIN_25~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_25~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_25~output .IN_POWERUP = 1'b0;
defparam \PIN_25~output .OUT_REG_MODE = 1'b0;
defparam \PIN_25~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_25~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_25~output .OUT_POWERUP = 1'b0;
defparam \PIN_25~output .OE_REG_MODE = 1'b0;
defparam \PIN_25~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_25~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_25~output .OE_POWERUP = 1'b0;
defparam \PIN_25~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_25~output .CFG_INPUT_EN = 1'b1;
defparam \PIN_25~output .CFG_PULL_UP = 1'b0;
defparam \PIN_25~output .CFG_SLR = 1'b0;
defparam \PIN_25~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_25~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_25~output .CFG_KEEP = 2'b00;
defparam \PIN_25~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_25~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_25~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_25~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_25~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_25~output .OUT_DELAY = 1'b0;
defparam \PIN_25~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_25~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_26~output (
	.padio(PIN_26),
	.datain(\rv32.gpio0_io_out_data[6] ),
	.oe(\rv32.gpio0_io_out_en[6] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_26~input_o ),
	.regout());
defparam \PIN_26~output .coord_x = 18;
defparam \PIN_26~output .coord_y = 13;
defparam \PIN_26~output .coord_z = 0;
defparam \PIN_26~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_26~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_26~output .IN_POWERUP = 1'b0;
defparam \PIN_26~output .OUT_REG_MODE = 1'b0;
defparam \PIN_26~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_26~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_26~output .OUT_POWERUP = 1'b0;
defparam \PIN_26~output .OE_REG_MODE = 1'b0;
defparam \PIN_26~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_26~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_26~output .OE_POWERUP = 1'b0;
defparam \PIN_26~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_26~output .CFG_INPUT_EN = 1'b1;
defparam \PIN_26~output .CFG_PULL_UP = 1'b0;
defparam \PIN_26~output .CFG_SLR = 1'b0;
defparam \PIN_26~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_26~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_26~output .CFG_KEEP = 2'b00;
defparam \PIN_26~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_26~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_26~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_26~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_26~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_26~output .OUT_DELAY = 1'b0;
defparam \PIN_26~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_26~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_33~output (
	.padio(PIN_33),
	.datain(\rv32.gpio0_io_out_data[5] ),
	.oe(\rv32.gpio0_io_out_en[5] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_33~input_o ),
	.regout());
defparam \PIN_33~output .coord_x = 0;
defparam \PIN_33~output .coord_y = 4;
defparam \PIN_33~output .coord_z = 0;
defparam \PIN_33~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_33~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_33~output .IN_POWERUP = 1'b0;
defparam \PIN_33~output .OUT_REG_MODE = 1'b0;
defparam \PIN_33~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_33~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_33~output .OUT_POWERUP = 1'b0;
defparam \PIN_33~output .OE_REG_MODE = 1'b0;
defparam \PIN_33~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_33~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_33~output .OE_POWERUP = 1'b0;
defparam \PIN_33~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_33~output .CFG_INPUT_EN = 1'b1;
defparam \PIN_33~output .CFG_PULL_UP = 1'b0;
defparam \PIN_33~output .CFG_SLR = 1'b0;
defparam \PIN_33~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_33~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_33~output .CFG_KEEP = 2'b00;
defparam \PIN_33~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_33~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_33~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_33~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_33~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_33~output .OUT_DELAY = 1'b0;
defparam \PIN_33~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_33~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_34~output (
	.padio(PIN_34),
	.datain(\rv32.gpio5_io_out_data[0] ),
	.oe(\rv32.gpio5_io_out_en[0] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout());
defparam \PIN_34~output .coord_x = 0;
defparam \PIN_34~output .coord_y = 4;
defparam \PIN_34~output .coord_z = 1;
defparam \PIN_34~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_34~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_34~output .IN_POWERUP = 1'b0;
defparam \PIN_34~output .OUT_REG_MODE = 1'b0;
defparam \PIN_34~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_34~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_34~output .OUT_POWERUP = 1'b0;
defparam \PIN_34~output .OE_REG_MODE = 1'b0;
defparam \PIN_34~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_34~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_34~output .OE_POWERUP = 1'b0;
defparam \PIN_34~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_34~output .CFG_INPUT_EN = 1'b0;
defparam \PIN_34~output .CFG_PULL_UP = 1'b0;
defparam \PIN_34~output .CFG_SLR = 1'b0;
defparam \PIN_34~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_34~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_34~output .CFG_KEEP = 2'b00;
defparam \PIN_34~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_34~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_34~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_34~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_34~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_34~output .OUT_DELAY = 1'b0;
defparam \PIN_34~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_34~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_35~output (
	.padio(PIN_35),
	.datain(\rv32.gpio3_io_out_data[0] ),
	.oe(\rv32.gpio3_io_out_en[0] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_35~input_o ),
	.regout());
defparam \PIN_35~output .coord_x = 0;
defparam \PIN_35~output .coord_y = 4;
defparam \PIN_35~output .coord_z = 2;
defparam \PIN_35~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_35~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_35~output .IN_POWERUP = 1'b0;
defparam \PIN_35~output .OUT_REG_MODE = 1'b0;
defparam \PIN_35~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_35~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_35~output .OUT_POWERUP = 1'b0;
defparam \PIN_35~output .OE_REG_MODE = 1'b0;
defparam \PIN_35~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_35~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_35~output .OE_POWERUP = 1'b0;
defparam \PIN_35~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_35~output .CFG_INPUT_EN = 1'b1;
defparam \PIN_35~output .CFG_PULL_UP = 1'b0;
defparam \PIN_35~output .CFG_SLR = 1'b0;
defparam \PIN_35~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_35~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_35~output .CFG_KEEP = 2'b00;
defparam \PIN_35~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_35~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_35~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_35~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_35~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_35~output .OUT_DELAY = 1'b0;
defparam \PIN_35~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_35~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_36~output (
	.padio(PIN_36),
	.datain(\rv32.gpio3_io_out_data[1] ),
	.oe(\rv32.gpio3_io_out_en[1] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_36~input_o ),
	.regout());
defparam \PIN_36~output .coord_x = 0;
defparam \PIN_36~output .coord_y = 4;
defparam \PIN_36~output .coord_z = 3;
defparam \PIN_36~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_36~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_36~output .IN_POWERUP = 1'b0;
defparam \PIN_36~output .OUT_REG_MODE = 1'b0;
defparam \PIN_36~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_36~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_36~output .OUT_POWERUP = 1'b0;
defparam \PIN_36~output .OE_REG_MODE = 1'b0;
defparam \PIN_36~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_36~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_36~output .OE_POWERUP = 1'b0;
defparam \PIN_36~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_36~output .CFG_INPUT_EN = 1'b1;
defparam \PIN_36~output .CFG_PULL_UP = 1'b0;
defparam \PIN_36~output .CFG_SLR = 1'b0;
defparam \PIN_36~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_36~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_36~output .CFG_KEEP = 2'b00;
defparam \PIN_36~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_36~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_36~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_36~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_36~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_36~output .OUT_DELAY = 1'b0;
defparam \PIN_36~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_36~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_37~output (
	.padio(PIN_37),
	.datain(\rv32.gpio6_io_out_data[5] ),
	.oe(\rv32.gpio6_io_out_en[5] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_37~input_o ),
	.regout());
defparam \PIN_37~output .coord_x = 0;
defparam \PIN_37~output .coord_y = 2;
defparam \PIN_37~output .coord_z = 0;
defparam \PIN_37~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_37~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_37~output .IN_POWERUP = 1'b0;
defparam \PIN_37~output .OUT_REG_MODE = 1'b0;
defparam \PIN_37~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_37~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_37~output .OUT_POWERUP = 1'b0;
defparam \PIN_37~output .OE_REG_MODE = 1'b0;
defparam \PIN_37~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_37~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_37~output .OE_POWERUP = 1'b0;
defparam \PIN_37~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_37~output .CFG_INPUT_EN = 1'b1;
defparam \PIN_37~output .CFG_PULL_UP = 1'b0;
defparam \PIN_37~output .CFG_SLR = 1'b0;
defparam \PIN_37~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_37~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_37~output .CFG_KEEP = 2'b00;
defparam \PIN_37~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_37~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_37~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_37~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_37~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_37~output .OUT_DELAY = 1'b0;
defparam \PIN_37~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_37~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_38~output (
	.padio(PIN_38),
	.datain(\rv32.gpio6_io_out_data[4] ),
	.oe(\rv32.gpio6_io_out_en[4] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_38~input_o ),
	.regout());
defparam \PIN_38~output .coord_x = 0;
defparam \PIN_38~output .coord_y = 2;
defparam \PIN_38~output .coord_z = 1;
defparam \PIN_38~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_38~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_38~output .IN_POWERUP = 1'b0;
defparam \PIN_38~output .OUT_REG_MODE = 1'b0;
defparam \PIN_38~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_38~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_38~output .OUT_POWERUP = 1'b0;
defparam \PIN_38~output .OE_REG_MODE = 1'b0;
defparam \PIN_38~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_38~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_38~output .OE_POWERUP = 1'b0;
defparam \PIN_38~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_38~output .CFG_INPUT_EN = 1'b1;
defparam \PIN_38~output .CFG_PULL_UP = 1'b0;
defparam \PIN_38~output .CFG_SLR = 1'b0;
defparam \PIN_38~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_38~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_38~output .CFG_KEEP = 2'b00;
defparam \PIN_38~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_38~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_38~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_38~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_38~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_38~output .OUT_DELAY = 1'b0;
defparam \PIN_38~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_38~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_39~output (
	.padio(PIN_39),
	.datain(\rv32.gpio6_io_out_data[2] ),
	.oe(\rv32.gpio6_io_out_en[2] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_39~input_o ),
	.regout());
defparam \PIN_39~output .coord_x = 0;
defparam \PIN_39~output .coord_y = 2;
defparam \PIN_39~output .coord_z = 2;
defparam \PIN_39~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_39~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_39~output .IN_POWERUP = 1'b0;
defparam \PIN_39~output .OUT_REG_MODE = 1'b0;
defparam \PIN_39~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_39~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_39~output .OUT_POWERUP = 1'b0;
defparam \PIN_39~output .OE_REG_MODE = 1'b0;
defparam \PIN_39~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_39~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_39~output .OE_POWERUP = 1'b0;
defparam \PIN_39~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_39~output .CFG_INPUT_EN = 1'b1;
defparam \PIN_39~output .CFG_PULL_UP = 1'b0;
defparam \PIN_39~output .CFG_SLR = 1'b0;
defparam \PIN_39~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_39~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_39~output .CFG_KEEP = 2'b00;
defparam \PIN_39~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_39~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_39~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_39~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_39~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_39~output .OUT_DELAY = 1'b0;
defparam \PIN_39~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_39~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_40~output (
	.padio(PIN_40),
	.datain(\rv32.gpio6_io_out_data[0] ),
	.oe(\rv32.gpio6_io_out_en[0] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_40~input_o ),
	.regout());
defparam \PIN_40~output .coord_x = 0;
defparam \PIN_40~output .coord_y = 2;
defparam \PIN_40~output .coord_z = 3;
defparam \PIN_40~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_40~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_40~output .IN_POWERUP = 1'b0;
defparam \PIN_40~output .OUT_REG_MODE = 1'b0;
defparam \PIN_40~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_40~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_40~output .OUT_POWERUP = 1'b0;
defparam \PIN_40~output .OE_REG_MODE = 1'b0;
defparam \PIN_40~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_40~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_40~output .OE_POWERUP = 1'b0;
defparam \PIN_40~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_40~output .CFG_INPUT_EN = 1'b1;
defparam \PIN_40~output .CFG_PULL_UP = 1'b0;
defparam \PIN_40~output .CFG_SLR = 1'b0;
defparam \PIN_40~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_40~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_40~output .CFG_KEEP = 2'b00;
defparam \PIN_40~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_40~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_40~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_40~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_40~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_40~output .OUT_DELAY = 1'b0;
defparam \PIN_40~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_40~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_41~output (
	.padio(PIN_41),
	.datain(\rv32.gpio6_io_out_data[6] ),
	.oe(\rv32.gpio6_io_out_en[6] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_41~input_o ),
	.regout());
defparam \PIN_41~output .coord_x = 0;
defparam \PIN_41~output .coord_y = 2;
defparam \PIN_41~output .coord_z = 4;
defparam \PIN_41~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_41~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_41~output .IN_POWERUP = 1'b0;
defparam \PIN_41~output .OUT_REG_MODE = 1'b0;
defparam \PIN_41~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_41~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_41~output .OUT_POWERUP = 1'b0;
defparam \PIN_41~output .OE_REG_MODE = 1'b0;
defparam \PIN_41~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_41~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_41~output .OE_POWERUP = 1'b0;
defparam \PIN_41~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_41~output .CFG_INPUT_EN = 1'b1;
defparam \PIN_41~output .CFG_PULL_UP = 1'b0;
defparam \PIN_41~output .CFG_SLR = 1'b0;
defparam \PIN_41~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_41~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_41~output .CFG_KEEP = 2'b00;
defparam \PIN_41~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_41~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_41~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_41~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_41~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_41~output .OUT_DELAY = 1'b0;
defparam \PIN_41~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_41~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_42~output (
	.padio(PIN_42),
	.datain(\rv32.gpio4_io_out_data[6] ),
	.oe(\rv32.gpio4_io_out_en[6] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout());
defparam \PIN_42~output .coord_x = 0;
defparam \PIN_42~output .coord_y = 2;
defparam \PIN_42~output .coord_z = 5;
defparam \PIN_42~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_42~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_42~output .IN_POWERUP = 1'b0;
defparam \PIN_42~output .OUT_REG_MODE = 1'b0;
defparam \PIN_42~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_42~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_42~output .OUT_POWERUP = 1'b0;
defparam \PIN_42~output .OE_REG_MODE = 1'b0;
defparam \PIN_42~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_42~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_42~output .OE_POWERUP = 1'b0;
defparam \PIN_42~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_42~output .CFG_INPUT_EN = 1'b0;
defparam \PIN_42~output .CFG_PULL_UP = 1'b0;
defparam \PIN_42~output .CFG_SLR = 1'b0;
defparam \PIN_42~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_42~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_42~output .CFG_KEEP = 2'b00;
defparam \PIN_42~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_42~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_42~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_42~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_42~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_42~output .OUT_DELAY = 1'b0;
defparam \PIN_42~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_42~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_43~output (
	.padio(PIN_43),
	.datain(\rv32.gpio0_io_out_data[1] ),
	.oe(\rv32.gpio0_io_out_en[1] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_43~input_o ),
	.regout());
defparam \PIN_43~output .coord_x = 0;
defparam \PIN_43~output .coord_y = 1;
defparam \PIN_43~output .coord_z = 0;
defparam \PIN_43~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_43~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_43~output .IN_POWERUP = 1'b0;
defparam \PIN_43~output .OUT_REG_MODE = 1'b0;
defparam \PIN_43~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_43~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_43~output .OUT_POWERUP = 1'b0;
defparam \PIN_43~output .OE_REG_MODE = 1'b0;
defparam \PIN_43~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_43~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_43~output .OE_POWERUP = 1'b0;
defparam \PIN_43~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_43~output .CFG_INPUT_EN = 1'b1;
defparam \PIN_43~output .CFG_PULL_UP = 1'b0;
defparam \PIN_43~output .CFG_SLR = 1'b0;
defparam \PIN_43~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_43~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_43~output .CFG_KEEP = 2'b00;
defparam \PIN_43~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_43~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_43~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_43~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_43~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_43~output .OUT_DELAY = 1'b0;
defparam \PIN_43~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_43~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_44~output (
	.padio(PIN_44),
	.datain(\rv32.gpio4_io_out_data[5] ),
	.oe(\rv32.gpio4_io_out_en[5] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout());
defparam \PIN_44~output .coord_x = 0;
defparam \PIN_44~output .coord_y = 1;
defparam \PIN_44~output .coord_z = 2;
defparam \PIN_44~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_44~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_44~output .IN_POWERUP = 1'b0;
defparam \PIN_44~output .OUT_REG_MODE = 1'b0;
defparam \PIN_44~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_44~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_44~output .OUT_POWERUP = 1'b0;
defparam \PIN_44~output .OE_REG_MODE = 1'b0;
defparam \PIN_44~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_44~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_44~output .OE_POWERUP = 1'b0;
defparam \PIN_44~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_44~output .CFG_INPUT_EN = 1'b0;
defparam \PIN_44~output .CFG_PULL_UP = 1'b0;
defparam \PIN_44~output .CFG_SLR = 1'b0;
defparam \PIN_44~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_44~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_44~output .CFG_KEEP = 2'b00;
defparam \PIN_44~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_44~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_44~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_44~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_44~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_44~output .OUT_DELAY = 1'b0;
defparam \PIN_44~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_44~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_45~output (
	.padio(PIN_45),
	.datain(\rv32.gpio0_io_out_data[0] ),
	.oe(\rv32.gpio0_io_out_en[0] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_45~input_o ),
	.regout());
defparam \PIN_45~output .coord_x = 0;
defparam \PIN_45~output .coord_y = 1;
defparam \PIN_45~output .coord_z = 3;
defparam \PIN_45~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_45~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_45~output .IN_POWERUP = 1'b0;
defparam \PIN_45~output .OUT_REG_MODE = 1'b0;
defparam \PIN_45~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_45~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_45~output .OUT_POWERUP = 1'b0;
defparam \PIN_45~output .OE_REG_MODE = 1'b0;
defparam \PIN_45~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_45~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_45~output .OE_POWERUP = 1'b0;
defparam \PIN_45~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_45~output .CFG_INPUT_EN = 1'b1;
defparam \PIN_45~output .CFG_PULL_UP = 1'b0;
defparam \PIN_45~output .CFG_SLR = 1'b0;
defparam \PIN_45~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_45~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_45~output .CFG_KEEP = 2'b00;
defparam \PIN_45~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_45~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_45~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_45~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_45~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_45~output .OUT_DELAY = 1'b0;
defparam \PIN_45~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_45~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_47~output (
	.padio(PIN_47),
	.datain(\rv32.gpio0_io_out_data[3] ),
	.oe(\rv32.gpio0_io_out_en[3] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_47~input_o ),
	.regout());
defparam \PIN_47~output .coord_x = 0;
defparam \PIN_47~output .coord_y = 1;
defparam \PIN_47~output .coord_z = 5;
defparam \PIN_47~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_47~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_47~output .IN_POWERUP = 1'b0;
defparam \PIN_47~output .OUT_REG_MODE = 1'b0;
defparam \PIN_47~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_47~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_47~output .OUT_POWERUP = 1'b0;
defparam \PIN_47~output .OE_REG_MODE = 1'b0;
defparam \PIN_47~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_47~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_47~output .OE_POWERUP = 1'b0;
defparam \PIN_47~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_47~output .CFG_INPUT_EN = 1'b1;
defparam \PIN_47~output .CFG_PULL_UP = 1'b0;
defparam \PIN_47~output .CFG_SLR = 1'b0;
defparam \PIN_47~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_47~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_47~output .CFG_KEEP = 2'b00;
defparam \PIN_47~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_47~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_47~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_47~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_47~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_47~output .OUT_DELAY = 1'b0;
defparam \PIN_47~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_47~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_52~output (
	.padio(PIN_52),
	.datain(\rv32.gpio7_io_out_data[6] ),
	.oe(\rv32.gpio7_io_out_en[6] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout());
defparam \PIN_52~output .coord_x = 1;
defparam \PIN_52~output .coord_y = 0;
defparam \PIN_52~output .coord_z = 3;
defparam \PIN_52~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_52~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_52~output .IN_POWERUP = 1'b0;
defparam \PIN_52~output .OUT_REG_MODE = 1'b0;
defparam \PIN_52~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_52~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_52~output .OUT_POWERUP = 1'b0;
defparam \PIN_52~output .OE_REG_MODE = 1'b0;
defparam \PIN_52~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_52~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_52~output .OE_POWERUP = 1'b0;
defparam \PIN_52~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_52~output .CFG_INPUT_EN = 1'b0;
defparam \PIN_52~output .CFG_PULL_UP = 1'b0;
defparam \PIN_52~output .CFG_SLR = 1'b0;
defparam \PIN_52~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_52~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_52~output .CFG_KEEP = 2'b00;
defparam \PIN_52~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_52~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_52~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_52~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_52~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_52~output .OUT_DELAY = 1'b0;
defparam \PIN_52~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_52~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_53~input (
	.padio(PIN_53),
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_53~input_o ),
	.regout());
defparam \PIN_53~input .coord_x = 6;
defparam \PIN_53~input .coord_y = 0;
defparam \PIN_53~input .coord_z = 0;
defparam \PIN_53~input .IN_ASYNC_MODE = 1'b0;
defparam \PIN_53~input .IN_SYNC_MODE = 1'b0;
defparam \PIN_53~input .IN_POWERUP = 1'b0;
defparam \PIN_53~input .OUT_REG_MODE = 1'b0;
defparam \PIN_53~input .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_53~input .OUT_SYNC_MODE = 1'b0;
defparam \PIN_53~input .OUT_POWERUP = 1'b0;
defparam \PIN_53~input .OE_REG_MODE = 1'b0;
defparam \PIN_53~input .OE_ASYNC_MODE = 1'b0;
defparam \PIN_53~input .OE_SYNC_MODE = 1'b0;
defparam \PIN_53~input .OE_POWERUP = 1'b0;
defparam \PIN_53~input .CFG_TRI_INPUT = 1'b0;
defparam \PIN_53~input .CFG_INPUT_EN = 1'b1;
defparam \PIN_53~input .CFG_PULL_UP = 1'b0;
defparam \PIN_53~input .CFG_SLR = 1'b0;
defparam \PIN_53~input .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_53~input .CFG_PDRCTRL = 4'b0100;
defparam \PIN_53~input .CFG_KEEP = 2'b00;
defparam \PIN_53~input .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_53~input .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_53~input .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_53~input .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_53~input .DPCLK_DELAY = 4'b0000;
defparam \PIN_53~input .OUT_DELAY = 1'b0;
defparam \PIN_53~input .IN_DATA_DELAY = 3'b000;
defparam \PIN_53~input .IN_REG_DELAY = 3'b000;

alta_rio \PIN_54~output (
	.padio(PIN_54),
	.datain(\rv32.gpio5_io_out_data[0] ),
	.oe(\rv32.gpio5_io_out_en[0] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_54~input_o ),
	.regout());
defparam \PIN_54~output .coord_x = 7;
defparam \PIN_54~output .coord_y = 0;
defparam \PIN_54~output .coord_z = 1;
defparam \PIN_54~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_54~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_54~output .IN_POWERUP = 1'b0;
defparam \PIN_54~output .OUT_REG_MODE = 1'b0;
defparam \PIN_54~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_54~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_54~output .OUT_POWERUP = 1'b0;
defparam \PIN_54~output .OE_REG_MODE = 1'b0;
defparam \PIN_54~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_54~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_54~output .OE_POWERUP = 1'b0;
defparam \PIN_54~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_54~output .CFG_INPUT_EN = 1'b1;
defparam \PIN_54~output .CFG_PULL_UP = 1'b0;
defparam \PIN_54~output .CFG_SLR = 1'b0;
defparam \PIN_54~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_54~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_54~output .CFG_KEEP = 2'b00;
defparam \PIN_54~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_54~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_54~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_54~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_54~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_54~output .OUT_DELAY = 1'b0;
defparam \PIN_54~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_54~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_55~output (
	.padio(PIN_55),
	.datain(\macro_inst|spi_inst|scs~q ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout());
defparam \PIN_55~output .coord_x = 17;
defparam \PIN_55~output .coord_y = 0;
defparam \PIN_55~output .coord_z = 0;
defparam \PIN_55~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_55~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_55~output .IN_POWERUP = 1'b0;
defparam \PIN_55~output .OUT_REG_MODE = 1'b0;
defparam \PIN_55~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_55~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_55~output .OUT_POWERUP = 1'b0;
defparam \PIN_55~output .OE_REG_MODE = 1'b0;
defparam \PIN_55~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_55~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_55~output .OE_POWERUP = 1'b0;
defparam \PIN_55~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_55~output .CFG_INPUT_EN = 1'b0;
defparam \PIN_55~output .CFG_PULL_UP = 1'b0;
defparam \PIN_55~output .CFG_SLR = 1'b0;
defparam \PIN_55~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_55~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_55~output .CFG_KEEP = 2'b00;
defparam \PIN_55~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_55~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_55~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_55~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_55~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_55~output .OUT_DELAY = 1'b0;
defparam \PIN_55~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_55~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_56~output (
	.padio(PIN_56),
	.datain(\macro_inst|spi_inst|sck~q ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout());
defparam \PIN_56~output .coord_x = 17;
defparam \PIN_56~output .coord_y = 0;
defparam \PIN_56~output .coord_z = 1;
defparam \PIN_56~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_56~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_56~output .IN_POWERUP = 1'b0;
defparam \PIN_56~output .OUT_REG_MODE = 1'b0;
defparam \PIN_56~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_56~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_56~output .OUT_POWERUP = 1'b0;
defparam \PIN_56~output .OE_REG_MODE = 1'b0;
defparam \PIN_56~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_56~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_56~output .OE_POWERUP = 1'b0;
defparam \PIN_56~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_56~output .CFG_INPUT_EN = 1'b0;
defparam \PIN_56~output .CFG_PULL_UP = 1'b0;
defparam \PIN_56~output .CFG_SLR = 1'b0;
defparam \PIN_56~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_56~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_56~output .CFG_KEEP = 2'b00;
defparam \PIN_56~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_56~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_56~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_56~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_56~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_56~output .OUT_DELAY = 1'b0;
defparam \PIN_56~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_56~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_57~output (
	.padio(PIN_57),
	.datain(!\macro_inst|spi_inst|tx_data_r [7]),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout());
defparam \PIN_57~output .coord_x = 17;
defparam \PIN_57~output .coord_y = 0;
defparam \PIN_57~output .coord_z = 2;
defparam \PIN_57~output .IN_ASYNC_MODE = 1'b0;
defparam \PIN_57~output .IN_SYNC_MODE = 1'b0;
defparam \PIN_57~output .IN_POWERUP = 1'b0;
defparam \PIN_57~output .OUT_REG_MODE = 1'b0;
defparam \PIN_57~output .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_57~output .OUT_SYNC_MODE = 1'b0;
defparam \PIN_57~output .OUT_POWERUP = 1'b0;
defparam \PIN_57~output .OE_REG_MODE = 1'b0;
defparam \PIN_57~output .OE_ASYNC_MODE = 1'b0;
defparam \PIN_57~output .OE_SYNC_MODE = 1'b0;
defparam \PIN_57~output .OE_POWERUP = 1'b0;
defparam \PIN_57~output .CFG_TRI_INPUT = 1'b0;
defparam \PIN_57~output .CFG_INPUT_EN = 1'b0;
defparam \PIN_57~output .CFG_PULL_UP = 1'b0;
defparam \PIN_57~output .CFG_SLR = 1'b0;
defparam \PIN_57~output .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_57~output .CFG_PDRCTRL = 4'b0100;
defparam \PIN_57~output .CFG_KEEP = 2'b00;
defparam \PIN_57~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_57~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_57~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_57~output .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_57~output .DPCLK_DELAY = 4'b0000;
defparam \PIN_57~output .OUT_DELAY = 1'b0;
defparam \PIN_57~output .IN_DATA_DELAY = 3'b000;
defparam \PIN_57~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_58~input (
	.padio(PIN_58),
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_58~input_o ),
	.regout());
defparam \PIN_58~input .coord_x = 18;
defparam \PIN_58~input .coord_y = 0;
defparam \PIN_58~input .coord_z = 0;
defparam \PIN_58~input .IN_ASYNC_MODE = 1'b0;
defparam \PIN_58~input .IN_SYNC_MODE = 1'b0;
defparam \PIN_58~input .IN_POWERUP = 1'b0;
defparam \PIN_58~input .OUT_REG_MODE = 1'b0;
defparam \PIN_58~input .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_58~input .OUT_SYNC_MODE = 1'b0;
defparam \PIN_58~input .OUT_POWERUP = 1'b0;
defparam \PIN_58~input .OE_REG_MODE = 1'b0;
defparam \PIN_58~input .OE_ASYNC_MODE = 1'b0;
defparam \PIN_58~input .OE_SYNC_MODE = 1'b0;
defparam \PIN_58~input .OE_POWERUP = 1'b0;
defparam \PIN_58~input .CFG_TRI_INPUT = 1'b0;
defparam \PIN_58~input .CFG_INPUT_EN = 1'b1;
defparam \PIN_58~input .CFG_PULL_UP = 1'b0;
defparam \PIN_58~input .CFG_SLR = 1'b0;
defparam \PIN_58~input .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_58~input .CFG_PDRCTRL = 4'b0100;
defparam \PIN_58~input .CFG_KEEP = 2'b00;
defparam \PIN_58~input .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_58~input .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_58~input .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_58~input .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_58~input .DPCLK_DELAY = 4'b0000;
defparam \PIN_58~input .OUT_DELAY = 1'b0;
defparam \PIN_58~input .IN_DATA_DELAY = 3'b000;
defparam \PIN_58~input .IN_REG_DELAY = 3'b000;

alta_rio \PIN_HSE~input (
	.padio(PIN_HSE),
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_HSE~input_o ),
	.regout());
defparam \PIN_HSE~input .coord_x = 22;
defparam \PIN_HSE~input .coord_y = 4;
defparam \PIN_HSE~input .coord_z = 1;
defparam \PIN_HSE~input .IN_ASYNC_MODE = 1'b0;
defparam \PIN_HSE~input .IN_SYNC_MODE = 1'b0;
defparam \PIN_HSE~input .IN_POWERUP = 1'b0;
defparam \PIN_HSE~input .OUT_REG_MODE = 1'b0;
defparam \PIN_HSE~input .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_HSE~input .OUT_SYNC_MODE = 1'b0;
defparam \PIN_HSE~input .OUT_POWERUP = 1'b0;
defparam \PIN_HSE~input .OE_REG_MODE = 1'b0;
defparam \PIN_HSE~input .OE_ASYNC_MODE = 1'b0;
defparam \PIN_HSE~input .OE_SYNC_MODE = 1'b0;
defparam \PIN_HSE~input .OE_POWERUP = 1'b0;
defparam \PIN_HSE~input .CFG_TRI_INPUT = 1'b0;
defparam \PIN_HSE~input .CFG_PULL_UP = 1'b0;
defparam \PIN_HSE~input .CFG_SLR = 1'b0;
defparam \PIN_HSE~input .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_HSE~input .CFG_PDRCTRL = 4'b0010;
defparam \PIN_HSE~input .CFG_KEEP = 2'b00;
defparam \PIN_HSE~input .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_HSE~input .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_HSE~input .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_HSE~input .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_HSE~input .DPCLK_DELAY = 4'b0000;
defparam \PIN_HSE~input .OUT_DELAY = 1'b0;
defparam \PIN_HSE~input .IN_DATA_DELAY = 3'b000;
defparam \PIN_HSE~input .IN_REG_DELAY = 3'b000;

alta_rio \PIN_HSI~input (
	.padio(PIN_HSI),
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_HSI~input_o ),
	.regout());
defparam \PIN_HSI~input .coord_x = 22;
defparam \PIN_HSI~input .coord_y = 4;
defparam \PIN_HSI~input .coord_z = 0;
defparam \PIN_HSI~input .IN_ASYNC_MODE = 1'b0;
defparam \PIN_HSI~input .IN_SYNC_MODE = 1'b0;
defparam \PIN_HSI~input .IN_POWERUP = 1'b0;
defparam \PIN_HSI~input .OUT_REG_MODE = 1'b0;
defparam \PIN_HSI~input .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_HSI~input .OUT_SYNC_MODE = 1'b0;
defparam \PIN_HSI~input .OUT_POWERUP = 1'b0;
defparam \PIN_HSI~input .OE_REG_MODE = 1'b0;
defparam \PIN_HSI~input .OE_ASYNC_MODE = 1'b0;
defparam \PIN_HSI~input .OE_SYNC_MODE = 1'b0;
defparam \PIN_HSI~input .OE_POWERUP = 1'b0;
defparam \PIN_HSI~input .CFG_TRI_INPUT = 1'b0;
defparam \PIN_HSI~input .CFG_PULL_UP = 1'b0;
defparam \PIN_HSI~input .CFG_SLR = 1'b0;
defparam \PIN_HSI~input .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_HSI~input .CFG_PDRCTRL = 4'b0010;
defparam \PIN_HSI~input .CFG_KEEP = 2'b00;
defparam \PIN_HSI~input .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_HSI~input .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_HSI~input .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_HSI~input .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_HSI~input .DPCLK_DELAY = 4'b0000;
defparam \PIN_HSI~input .OUT_DELAY = 1'b0;
defparam \PIN_HSI~input .IN_DATA_DELAY = 3'b000;
defparam \PIN_HSI~input .IN_REG_DELAY = 3'b000;

alta_rio \PIN_OSC~input (
	.padio(PIN_OSC),
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_OSC~input_o ),
	.regout());
defparam \PIN_OSC~input .coord_x = 22;
defparam \PIN_OSC~input .coord_y = 4;
defparam \PIN_OSC~input .coord_z = 2;
defparam \PIN_OSC~input .IN_ASYNC_MODE = 1'b0;
defparam \PIN_OSC~input .IN_SYNC_MODE = 1'b0;
defparam \PIN_OSC~input .IN_POWERUP = 1'b0;
defparam \PIN_OSC~input .OUT_REG_MODE = 1'b0;
defparam \PIN_OSC~input .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_OSC~input .OUT_SYNC_MODE = 1'b0;
defparam \PIN_OSC~input .OUT_POWERUP = 1'b0;
defparam \PIN_OSC~input .OE_REG_MODE = 1'b0;
defparam \PIN_OSC~input .OE_ASYNC_MODE = 1'b0;
defparam \PIN_OSC~input .OE_SYNC_MODE = 1'b0;
defparam \PIN_OSC~input .OE_POWERUP = 1'b0;
defparam \PIN_OSC~input .CFG_TRI_INPUT = 1'b0;
defparam \PIN_OSC~input .CFG_PULL_UP = 1'b0;
defparam \PIN_OSC~input .CFG_SLR = 1'b0;
defparam \PIN_OSC~input .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_OSC~input .CFG_PDRCTRL = 4'b0010;
defparam \PIN_OSC~input .CFG_KEEP = 2'b00;
defparam \PIN_OSC~input .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_OSC~input .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_OSC~input .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_OSC~input .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_OSC~input .DPCLK_DELAY = 4'b0000;
defparam \PIN_OSC~input .OUT_DELAY = 1'b0;
defparam \PIN_OSC~input .IN_DATA_DELAY = 3'b000;
defparam \PIN_OSC~input .IN_REG_DELAY = 3'b000;

alta_slice PLL_ENABLE(
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\rv32.sys_ctrl_pllEnable ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\PLL_ENABLE~combout ),
	.Cout(),
	.Q());
defparam PLL_ENABLE.coord_x = 16;
defparam PLL_ENABLE.coord_y = 2;
defparam PLL_ENABLE.coord_z = 8;
defparam PLL_ENABLE.mask = 16'h00FF;
defparam PLL_ENABLE.modeMux = 1'b0;
defparam PLL_ENABLE.FeedbackMux = 1'b0;
defparam PLL_ENABLE.ShiftMux = 1'b0;
defparam PLL_ENABLE.BypassEn = 1'b0;
defparam PLL_ENABLE.CarryEnb = 1'b1;

alta_io_gclk \PLL_ENABLE~clkctrl (
	.inclk(\PLL_ENABLE~combout ),
	.outclk(\PLL_ENABLE~clkctrl_outclk ));
defparam \PLL_ENABLE~clkctrl .coord_x = 22;
defparam \PLL_ENABLE~clkctrl .coord_y = 4;
defparam \PLL_ENABLE~clkctrl .coord_z = 4;

alta_slice PLL_LOCK(
	.A(vcc),
	.B(\pll_inst|auto_generated|pll_lock_sync~q ),
	.C(vcc),
	.D(\auto_generated_inst.hbo_13_7ba00b93ceceb4ca_bp ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\PLL_LOCK~combout ),
	.Cout(),
	.Q());
defparam PLL_LOCK.coord_x = 16;
defparam PLL_LOCK.coord_y = 2;
defparam PLL_LOCK.coord_z = 9;
defparam PLL_LOCK.mask = 16'hCC00;
defparam PLL_LOCK.modeMux = 1'b0;
defparam PLL_LOCK.FeedbackMux = 1'b0;
defparam PLL_LOCK.ShiftMux = 1'b0;
defparam PLL_LOCK.BypassEn = 1'b0;
defparam PLL_LOCK.CarryEnb = 1'b1;

alta_asyncctrl asyncreset_ctrl_X48_Y2_N0(
	.Din(\PLL_ENABLE~clkctrl_outclk ),
	.Dout(\PLL_ENABLE~clkctrl_outclk__AsyncReset_X48_Y2_SIG ));
defparam asyncreset_ctrl_X48_Y2_N0.coord_x = 16;
defparam asyncreset_ctrl_X48_Y2_N0.coord_y = 2;
defparam asyncreset_ctrl_X48_Y2_N0.coord_z = 0;
defparam asyncreset_ctrl_X48_Y2_N0.AsyncCtrlMux = 2'b10;

alta_asyncctrl asyncreset_ctrl_X49_Y2_N0(
	.Din(),
	.Dout(AsyncReset_X49_Y2_GND));
defparam asyncreset_ctrl_X49_Y2_N0.coord_x = 15;
defparam asyncreset_ctrl_X49_Y2_N0.coord_y = 2;
defparam asyncreset_ctrl_X49_Y2_N0.coord_z = 0;
defparam asyncreset_ctrl_X49_Y2_N0.AsyncCtrlMux = 2'b00;

alta_asyncctrl asyncreset_ctrl_X50_Y2_N0(
	.Din(),
	.Dout(AsyncReset_X50_Y2_GND));
defparam asyncreset_ctrl_X50_Y2_N0.coord_x = 14;
defparam asyncreset_ctrl_X50_Y2_N0.coord_y = 2;
defparam asyncreset_ctrl_X50_Y2_N0.coord_z = 0;
defparam asyncreset_ctrl_X50_Y2_N0.AsyncCtrlMux = 2'b00;

alta_asyncctrl asyncreset_ctrl_X51_Y1_N0(
	.Din(),
	.Dout(AsyncReset_X51_Y1_GND));
defparam asyncreset_ctrl_X51_Y1_N0.coord_x = 17;
defparam asyncreset_ctrl_X51_Y1_N0.coord_y = 3;
defparam asyncreset_ctrl_X51_Y1_N0.coord_z = 0;
defparam asyncreset_ctrl_X51_Y1_N0.AsyncCtrlMux = 2'b00;

alta_asyncctrl asyncreset_ctrl_X51_Y2_N0(
	.Din(\sys_resetn~combout ),
	.Dout(\sys_resetn~combout__AsyncReset_X51_Y2_SIG ));
defparam asyncreset_ctrl_X51_Y2_N0.coord_x = 14;
defparam asyncreset_ctrl_X51_Y2_N0.coord_y = 5;
defparam asyncreset_ctrl_X51_Y2_N0.coord_z = 0;
defparam asyncreset_ctrl_X51_Y2_N0.AsyncCtrlMux = 2'b10;

alta_asyncctrl asyncreset_ctrl_X52_Y1_N0(
	.Din(),
	.Dout(AsyncReset_X52_Y1_GND));
defparam asyncreset_ctrl_X52_Y1_N0.coord_x = 16;
defparam asyncreset_ctrl_X52_Y1_N0.coord_y = 3;
defparam asyncreset_ctrl_X52_Y1_N0.coord_z = 0;
defparam asyncreset_ctrl_X52_Y1_N0.AsyncCtrlMux = 2'b00;

alta_asyncctrl asyncreset_ctrl_X52_Y2_N0(
	.Din(\sys_resetn~combout ),
	.Dout(\sys_resetn~combout__AsyncReset_X52_Y2_SIG ));
defparam asyncreset_ctrl_X52_Y2_N0.coord_x = 15;
defparam asyncreset_ctrl_X52_Y2_N0.coord_y = 5;
defparam asyncreset_ctrl_X52_Y2_N0.coord_z = 0;
defparam asyncreset_ctrl_X52_Y2_N0.AsyncCtrlMux = 2'b10;

alta_asyncctrl asyncreset_ctrl_X52_Y2_N1(
	.Din(),
	.Dout(AsyncReset_X52_Y2_GND));
defparam asyncreset_ctrl_X52_Y2_N1.coord_x = 15;
defparam asyncreset_ctrl_X52_Y2_N1.coord_y = 5;
defparam asyncreset_ctrl_X52_Y2_N1.coord_z = 1;
defparam asyncreset_ctrl_X52_Y2_N1.AsyncCtrlMux = 2'b00;

alta_asyncctrl asyncreset_ctrl_X53_Y1_N0(
	.Din(),
	.Dout(AsyncReset_X53_Y1_GND));
defparam asyncreset_ctrl_X53_Y1_N0.coord_x = 15;
defparam asyncreset_ctrl_X53_Y1_N0.coord_y = 4;
defparam asyncreset_ctrl_X53_Y1_N0.coord_z = 0;
defparam asyncreset_ctrl_X53_Y1_N0.AsyncCtrlMux = 2'b00;

alta_asyncctrl asyncreset_ctrl_X53_Y2_N0(
	.Din(\sys_resetn~combout ),
	.Dout(\sys_resetn~combout__AsyncReset_X53_Y2_SIG ));
defparam asyncreset_ctrl_X53_Y2_N0.coord_x = 14;
defparam asyncreset_ctrl_X53_Y2_N0.coord_y = 6;
defparam asyncreset_ctrl_X53_Y2_N0.coord_z = 0;
defparam asyncreset_ctrl_X53_Y2_N0.AsyncCtrlMux = 2'b10;

alta_asyncctrl asyncreset_ctrl_X53_Y2_N1(
	.Din(),
	.Dout(AsyncReset_X53_Y2_GND));
defparam asyncreset_ctrl_X53_Y2_N1.coord_x = 14;
defparam asyncreset_ctrl_X53_Y2_N1.coord_y = 6;
defparam asyncreset_ctrl_X53_Y2_N1.coord_z = 1;
defparam asyncreset_ctrl_X53_Y2_N1.AsyncCtrlMux = 2'b00;

alta_asyncctrl asyncreset_ctrl_X54_Y1_N0(
	.Din(),
	.Dout(AsyncReset_X54_Y1_GND));
defparam asyncreset_ctrl_X54_Y1_N0.coord_x = 14;
defparam asyncreset_ctrl_X54_Y1_N0.coord_y = 4;
defparam asyncreset_ctrl_X54_Y1_N0.coord_z = 0;
defparam asyncreset_ctrl_X54_Y1_N0.AsyncCtrlMux = 2'b00;

alta_asyncctrl asyncreset_ctrl_X54_Y2_N0(
	.Din(),
	.Dout(AsyncReset_X54_Y2_GND));
defparam asyncreset_ctrl_X54_Y2_N0.coord_x = 14;
defparam asyncreset_ctrl_X54_Y2_N0.coord_y = 3;
defparam asyncreset_ctrl_X54_Y2_N0.coord_z = 0;
defparam asyncreset_ctrl_X54_Y2_N0.AsyncCtrlMux = 2'b00;

alta_asyncctrl asyncreset_ctrl_X56_Y1_N0(
	.Din(),
	.Dout(AsyncReset_X56_Y1_GND));
defparam asyncreset_ctrl_X56_Y1_N0.coord_x = 14;
defparam asyncreset_ctrl_X56_Y1_N0.coord_y = 7;
defparam asyncreset_ctrl_X56_Y1_N0.coord_z = 0;
defparam asyncreset_ctrl_X56_Y1_N0.AsyncCtrlMux = 2'b00;

alta_asyncctrl asyncreset_ctrl_X56_Y2_N0(
	.Din(\sys_resetn~combout ),
	.Dout(\sys_resetn~combout__AsyncReset_X56_Y2_SIG ));
defparam asyncreset_ctrl_X56_Y2_N0.coord_x = 14;
defparam asyncreset_ctrl_X56_Y2_N0.coord_y = 8;
defparam asyncreset_ctrl_X56_Y2_N0.coord_z = 0;
defparam asyncreset_ctrl_X56_Y2_N0.AsyncCtrlMux = 2'b10;

alta_asyncctrl asyncreset_ctrl_X56_Y2_N1(
	.Din(),
	.Dout(AsyncReset_X56_Y2_GND));
defparam asyncreset_ctrl_X56_Y2_N1.coord_x = 14;
defparam asyncreset_ctrl_X56_Y2_N1.coord_y = 8;
defparam asyncreset_ctrl_X56_Y2_N1.coord_z = 1;
defparam asyncreset_ctrl_X56_Y2_N1.AsyncCtrlMux = 2'b00;

alta_asyncctrl asyncreset_ctrl_X57_Y2_N0(
	.Din(),
	.Dout(AsyncReset_X57_Y2_GND));
defparam asyncreset_ctrl_X57_Y2_N0.coord_x = 15;
defparam asyncreset_ctrl_X57_Y2_N0.coord_y = 6;
defparam asyncreset_ctrl_X57_Y2_N0.coord_z = 0;
defparam asyncreset_ctrl_X57_Y2_N0.AsyncCtrlMux = 2'b00;

alta_asyncctrl asyncreset_ctrl_X58_Y2_N0(
	.Din(),
	.Dout(AsyncReset_X58_Y2_GND));
defparam asyncreset_ctrl_X58_Y2_N0.coord_x = 15;
defparam asyncreset_ctrl_X58_Y2_N0.coord_y = 3;
defparam asyncreset_ctrl_X58_Y2_N0.coord_z = 0;
defparam asyncreset_ctrl_X58_Y2_N0.AsyncCtrlMux = 2'b00;

alta_asyncctrl asyncreset_ctrl_X59_Y2_N0(
	.Din(),
	.Dout(AsyncReset_X59_Y2_GND));
defparam asyncreset_ctrl_X59_Y2_N0.coord_x = 12;
defparam asyncreset_ctrl_X59_Y2_N0.coord_y = 3;
defparam asyncreset_ctrl_X59_Y2_N0.coord_z = 0;
defparam asyncreset_ctrl_X59_Y2_N0.AsyncCtrlMux = 2'b00;

alta_clkenctrl clken_ctrl_X48_Y2_N0(
	.ClkIn(\auto_generated_inst.hbo_13_7ba00b93ceceb4ca_bp ),
	.ClkEn(),
	.ClkOut(\auto_generated_inst.hbo_13_7ba00b93ceceb4ca_bp_X48_Y2_SIG_VCC ));
defparam clken_ctrl_X48_Y2_N0.coord_x = 16;
defparam clken_ctrl_X48_Y2_N0.coord_y = 2;
defparam clken_ctrl_X48_Y2_N0.coord_z = 0;
defparam clken_ctrl_X48_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X48_Y2_N0.ClkEnMux = 2'b01;

alta_clkenctrl clken_ctrl_X49_Y2_N0(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X49_Y2_SIG_VCC ));
defparam clken_ctrl_X49_Y2_N0.coord_x = 15;
defparam clken_ctrl_X49_Y2_N0.coord_y = 2;
defparam clken_ctrl_X49_Y2_N0.coord_z = 0;
defparam clken_ctrl_X49_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X49_Y2_N0.ClkEnMux = 2'b01;

alta_clkenctrl clken_ctrl_X49_Y2_N1(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout_X49_Y2_SIG_SIG ));
defparam clken_ctrl_X49_Y2_N1.coord_x = 15;
defparam clken_ctrl_X49_Y2_N1.coord_y = 2;
defparam clken_ctrl_X49_Y2_N1.coord_z = 1;
defparam clken_ctrl_X49_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X49_Y2_N1.ClkEnMux = 2'b10;

alta_clkenctrl clken_ctrl_X50_Y2_N0(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(\macro_inst|spi_inst|sck_cnt[0]~0_combout ),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|sck_cnt[0]~0_combout_X50_Y2_SIG_SIG ));
defparam clken_ctrl_X50_Y2_N0.coord_x = 14;
defparam clken_ctrl_X50_Y2_N0.coord_y = 2;
defparam clken_ctrl_X50_Y2_N0.coord_z = 0;
defparam clken_ctrl_X50_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X50_Y2_N0.ClkEnMux = 2'b10;

alta_clkenctrl clken_ctrl_X50_Y2_N1(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X50_Y2_SIG_VCC ));
defparam clken_ctrl_X50_Y2_N1.coord_x = 14;
defparam clken_ctrl_X50_Y2_N1.coord_y = 2;
defparam clken_ctrl_X50_Y2_N1.coord_z = 1;
defparam clken_ctrl_X50_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X50_Y2_N1.ClkEnMux = 2'b01;

alta_clkenctrl clken_ctrl_X51_Y1_N0(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(\macro_inst|spi_inst|always9~0_combout ),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always9~0_combout_X51_Y1_SIG_SIG ));
defparam clken_ctrl_X51_Y1_N0.coord_x = 17;
defparam clken_ctrl_X51_Y1_N0.coord_y = 3;
defparam clken_ctrl_X51_Y1_N0.coord_z = 0;
defparam clken_ctrl_X51_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X51_Y1_N0.ClkEnMux = 2'b10;

alta_clkenctrl clken_ctrl_X51_Y1_N1(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(\macro_inst|spi_inst|always7~0_combout ),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always7~0_combout_X51_Y1_SIG_SIG ));
defparam clken_ctrl_X51_Y1_N1.coord_x = 17;
defparam clken_ctrl_X51_Y1_N1.coord_y = 3;
defparam clken_ctrl_X51_Y1_N1.coord_z = 1;
defparam clken_ctrl_X51_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X51_Y1_N1.ClkEnMux = 2'b10;

alta_clkenctrl clken_ctrl_X51_Y2_N0(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(\macro_inst|ahb2apb_inst|pwrite~0_combout ),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ahb2apb_inst|pwrite~0_combout_X51_Y2_SIG_SIG ));
defparam clken_ctrl_X51_Y2_N0.coord_x = 14;
defparam clken_ctrl_X51_Y2_N0.coord_y = 5;
defparam clken_ctrl_X51_Y2_N0.coord_z = 0;
defparam clken_ctrl_X51_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X51_Y2_N0.ClkEnMux = 2'b10;

alta_clkenctrl clken_ctrl_X51_Y2_N1(
	.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ),
	.ClkEn(\macro_inst|ahb2apb_inst|always0~0_combout ),
	.ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X51_Y2_SIG_SIG ));
defparam clken_ctrl_X51_Y2_N1.coord_x = 14;
defparam clken_ctrl_X51_Y2_N1.coord_y = 5;
defparam clken_ctrl_X51_Y2_N1.coord_z = 1;
defparam clken_ctrl_X51_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X51_Y2_N1.ClkEnMux = 2'b10;

alta_clkenctrl clken_ctrl_X52_Y1_N0(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y1_SIG_VCC ));
defparam clken_ctrl_X52_Y1_N0.coord_x = 16;
defparam clken_ctrl_X52_Y1_N0.coord_y = 3;
defparam clken_ctrl_X52_Y1_N0.coord_z = 0;
defparam clken_ctrl_X52_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X52_Y1_N0.ClkEnMux = 2'b01;

alta_clkenctrl clken_ctrl_X52_Y2_N0(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y2_SIG_VCC ));
defparam clken_ctrl_X52_Y2_N0.coord_x = 15;
defparam clken_ctrl_X52_Y2_N0.coord_y = 5;
defparam clken_ctrl_X52_Y2_N0.coord_z = 0;
defparam clken_ctrl_X52_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X52_Y2_N0.ClkEnMux = 2'b01;

alta_clkenctrl clken_ctrl_X52_Y2_N1(
	.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ),
	.ClkEn(),
	.ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X52_Y2_SIG_VCC ));
defparam clken_ctrl_X52_Y2_N1.coord_x = 15;
defparam clken_ctrl_X52_Y2_N1.coord_y = 5;
defparam clken_ctrl_X52_Y2_N1.coord_z = 1;
defparam clken_ctrl_X52_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X52_Y2_N1.ClkEnMux = 2'b01;

alta_clkenctrl clken_ctrl_X53_Y1_N0(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(\macro_inst|spi_inst|tx_data_r[7]~1_combout ),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|tx_data_r[7]~1_combout_X53_Y1_SIG_SIG ));
defparam clken_ctrl_X53_Y1_N0.coord_x = 15;
defparam clken_ctrl_X53_Y1_N0.coord_y = 4;
defparam clken_ctrl_X53_Y1_N0.coord_z = 0;
defparam clken_ctrl_X53_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X53_Y1_N0.ClkEnMux = 2'b10;

alta_clkenctrl clken_ctrl_X53_Y1_N1(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X53_Y1_SIG_VCC ));
defparam clken_ctrl_X53_Y1_N1.coord_x = 15;
defparam clken_ctrl_X53_Y1_N1.coord_y = 4;
defparam clken_ctrl_X53_Y1_N1.coord_z = 1;
defparam clken_ctrl_X53_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X53_Y1_N1.ClkEnMux = 2'b01;

alta_clkenctrl clken_ctrl_X53_Y2_N0(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(\macro_inst|ahb2apb_inst|comb~0_combout ),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ahb2apb_inst|comb~0_combout_X53_Y2_SIG_SIG ));
defparam clken_ctrl_X53_Y2_N0.coord_x = 14;
defparam clken_ctrl_X53_Y2_N0.coord_y = 6;
defparam clken_ctrl_X53_Y2_N0.coord_z = 0;
defparam clken_ctrl_X53_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X53_Y2_N0.ClkEnMux = 2'b10;

alta_clkenctrl clken_ctrl_X53_Y2_N1(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(\macro_inst|ren~0_combout ),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ren~0_combout_X53_Y2_SIG_SIG ));
defparam clken_ctrl_X53_Y2_N1.coord_x = 14;
defparam clken_ctrl_X53_Y2_N1.coord_y = 6;
defparam clken_ctrl_X53_Y2_N1.coord_z = 1;
defparam clken_ctrl_X53_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X53_Y2_N1.ClkEnMux = 2'b10;

alta_clkenctrl clken_ctrl_X54_Y1_N0(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y1_SIG_SIG ));
defparam clken_ctrl_X54_Y1_N0.coord_x = 14;
defparam clken_ctrl_X54_Y1_N0.coord_y = 4;
defparam clken_ctrl_X54_Y1_N0.coord_z = 0;
defparam clken_ctrl_X54_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X54_Y1_N0.ClkEnMux = 2'b10;

alta_clkenctrl clken_ctrl_X54_Y1_N1(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X54_Y1_SIG_VCC ));
defparam clken_ctrl_X54_Y1_N1.coord_x = 14;
defparam clken_ctrl_X54_Y1_N1.coord_y = 4;
defparam clken_ctrl_X54_Y1_N1.coord_z = 1;
defparam clken_ctrl_X54_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X54_Y1_N1.ClkEnMux = 2'b01;

alta_clkenctrl clken_ctrl_X54_Y2_N0(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X54_Y2_SIG_VCC ));
defparam clken_ctrl_X54_Y2_N0.coord_x = 14;
defparam clken_ctrl_X54_Y2_N0.coord_y = 3;
defparam clken_ctrl_X54_Y2_N0.coord_z = 0;
defparam clken_ctrl_X54_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X54_Y2_N0.ClkEnMux = 2'b01;

alta_clkenctrl clken_ctrl_X54_Y2_N1(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y2_SIG_SIG ));
defparam clken_ctrl_X54_Y2_N1.coord_x = 14;
defparam clken_ctrl_X54_Y2_N1.coord_y = 3;
defparam clken_ctrl_X54_Y2_N1.coord_z = 1;
defparam clken_ctrl_X54_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X54_Y2_N1.ClkEnMux = 2'b10;

alta_clkenctrl clken_ctrl_X56_Y1_N0(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X56_Y1_SIG_VCC ));
defparam clken_ctrl_X56_Y1_N0.coord_x = 14;
defparam clken_ctrl_X56_Y1_N0.coord_y = 7;
defparam clken_ctrl_X56_Y1_N0.coord_z = 0;
defparam clken_ctrl_X56_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y1_N0.ClkEnMux = 2'b01;

alta_clkenctrl clken_ctrl_X56_Y1_N1(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout_X56_Y1_SIG_SIG ));
defparam clken_ctrl_X56_Y1_N1.coord_x = 14;
defparam clken_ctrl_X56_Y1_N1.coord_y = 7;
defparam clken_ctrl_X56_Y1_N1.coord_z = 1;
defparam clken_ctrl_X56_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y1_N1.ClkEnMux = 2'b10;

alta_clkenctrl clken_ctrl_X56_Y2_N0(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(\macro_inst|ahb2apb_inst|comb~0_combout ),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y2_SIG_SIG ));
defparam clken_ctrl_X56_Y2_N0.coord_x = 14;
defparam clken_ctrl_X56_Y2_N0.coord_y = 8;
defparam clken_ctrl_X56_Y2_N0.coord_z = 0;
defparam clken_ctrl_X56_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y2_N0.ClkEnMux = 2'b10;

alta_clkenctrl clken_ctrl_X56_Y2_N1(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(\macro_inst|ren~0_combout ),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ren~0_combout_X56_Y2_SIG_SIG ));
defparam clken_ctrl_X56_Y2_N1.coord_x = 14;
defparam clken_ctrl_X56_Y2_N1.coord_y = 8;
defparam clken_ctrl_X56_Y2_N1.coord_z = 1;
defparam clken_ctrl_X56_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y2_N1.ClkEnMux = 2'b10;

alta_clkenctrl clken_ctrl_X57_Y2_N0(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X57_Y2_SIG_VCC ));
defparam clken_ctrl_X57_Y2_N0.coord_x = 15;
defparam clken_ctrl_X57_Y2_N0.coord_y = 6;
defparam clken_ctrl_X57_Y2_N0.coord_z = 0;
defparam clken_ctrl_X57_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y2_N0.ClkEnMux = 2'b01;

alta_clkenctrl clken_ctrl_X57_Y2_N1(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2_combout ),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2_combout_X57_Y2_SIG_SIG ));
defparam clken_ctrl_X57_Y2_N1.coord_x = 15;
defparam clken_ctrl_X57_Y2_N1.coord_y = 6;
defparam clken_ctrl_X57_Y2_N1.coord_z = 1;
defparam clken_ctrl_X57_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y2_N1.ClkEnMux = 2'b10;

alta_clkenctrl clken_ctrl_X58_Y2_N0(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout_X58_Y2_SIG_SIG ));
defparam clken_ctrl_X58_Y2_N0.coord_x = 15;
defparam clken_ctrl_X58_Y2_N0.coord_y = 3;
defparam clken_ctrl_X58_Y2_N0.coord_z = 0;
defparam clken_ctrl_X58_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y2_N0.ClkEnMux = 2'b10;

alta_clkenctrl clken_ctrl_X58_Y2_N1(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X58_Y2_SIG_VCC ));
defparam clken_ctrl_X58_Y2_N1.coord_x = 15;
defparam clken_ctrl_X58_Y2_N1.coord_y = 3;
defparam clken_ctrl_X58_Y2_N1.coord_z = 1;
defparam clken_ctrl_X58_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y2_N1.ClkEnMux = 2'b01;

alta_clkenctrl clken_ctrl_X59_Y2_N0(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X59_Y2_SIG_VCC ));
defparam clken_ctrl_X59_Y2_N0.coord_x = 12;
defparam clken_ctrl_X59_Y2_N0.coord_y = 3;
defparam clken_ctrl_X59_Y2_N0.coord_z = 0;
defparam clken_ctrl_X59_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y2_N0.ClkEnMux = 2'b01;

alta_clkenctrl clken_ctrl_X59_Y2_N1(
	.ClkIn(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~9_combout ),
	.ClkOut(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~9_combout_X59_Y2_SIG_SIG ));
defparam clken_ctrl_X59_Y2_N1.coord_x = 12;
defparam clken_ctrl_X59_Y2_N1.coord_y = 3;
defparam clken_ctrl_X59_Y2_N1.coord_z = 1;
defparam clken_ctrl_X59_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y2_N1.ClkEnMux = 2'b10;

alta_io_gclk \gclksw_inst|gclk_switch (
	.inclk(\gclksw_inst|gclk_switch__alta_gclksw__clkout ),
	.outclk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ));
defparam \gclksw_inst|gclk_switch .coord_x = 22;
defparam \gclksw_inst|gclk_switch .coord_y = 4;
defparam \gclksw_inst|gclk_switch .coord_z = 5;

alta_gclksw \gclksw_inst|gclk_switch__alta_gclksw (
	.resetn(\rv32.resetn_out ),
	.clkin0(\PIN_HSI~input_o ),
	.clkin1(\PIN_HSE~input_o ),
	.clkin2(\pll_inst|auto_generated|pll1_CLK_bus [0]),
	.clkin3(vcc),
	.select({\rv32.sys_ctrl_clkSource[1] , \rv32.sys_ctrl_clkSource[0] }),
	.clkout(\gclksw_inst|gclk_switch__alta_gclksw__clkout ));
defparam \gclksw_inst|gclk_switch__alta_gclksw .coord_x = 22;
defparam \gclksw_inst|gclk_switch__alta_gclksw .coord_y = 4;
defparam \gclksw_inst|gclk_switch__alta_gclksw .coord_z = 0;

alta_slice \macro_inst|ahb2apb_inst|always0~0 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|ahb2apb_inst|hreadyout~q ),
	.D(\rv32.mem_ahb_htrans[1] ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|always0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|ahb2apb_inst|always0~0 .coord_x = 14;
defparam \macro_inst|ahb2apb_inst|always0~0 .coord_y = 5;
defparam \macro_inst|ahb2apb_inst|always0~0 .coord_z = 1;
defparam \macro_inst|ahb2apb_inst|always0~0 .mask = 16'h0F00;
defparam \macro_inst|ahb2apb_inst|always0~0 .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|always0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|always0~0 .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|always0~0 .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|always0~0 .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|apbState.apbIdle (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|ahb2apb_inst|apbState.apbSetup~q ),
	.D(\macro_inst|ahb2apb_inst|pvalid~q ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|apbState.apbIdle~q ),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X52_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|apbState.apbIdle~q ));
defparam \macro_inst|ahb2apb_inst|apbState.apbIdle .coord_x = 15;
defparam \macro_inst|ahb2apb_inst|apbState.apbIdle .coord_y = 5;
defparam \macro_inst|ahb2apb_inst|apbState.apbIdle .coord_z = 11;
defparam \macro_inst|ahb2apb_inst|apbState.apbIdle .mask = 16'hFFF0;
defparam \macro_inst|ahb2apb_inst|apbState.apbIdle .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|apbState.apbIdle .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|apbState.apbIdle .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|apbState.apbIdle .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|apbState.apbIdle .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|apbState.apbSetup (
	.A(),
	.B(),
	.C(\macro_inst|ahb2apb_inst|pwrite~0_combout ),
	.D(),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|apbState.apbSetup~q ),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X52_Y2_SIG ),
	.SyncReset(SyncReset_X52_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X52_Y2_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|apbState.apbSetup~q ));
defparam \macro_inst|ahb2apb_inst|apbState.apbSetup .coord_x = 15;
defparam \macro_inst|ahb2apb_inst|apbState.apbSetup .coord_y = 5;
defparam \macro_inst|ahb2apb_inst|apbState.apbSetup .coord_z = 14;
defparam \macro_inst|ahb2apb_inst|apbState.apbSetup .mask = 16'hFFFF;
defparam \macro_inst|ahb2apb_inst|apbState.apbSetup .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|apbState.apbSetup .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|apbState.apbSetup .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|apbState.apbSetup .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|apbState.apbSetup .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|comb~0 (
	.A(vcc),
	.B(\macro_inst|ahb2apb_inst|psel~q ),
	.C(vcc),
	.D(\macro_inst|ahb2apb_inst|penable~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|comb~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|ahb2apb_inst|comb~0 .coord_x = 14;
defparam \macro_inst|ahb2apb_inst|comb~0 .coord_y = 6;
defparam \macro_inst|ahb2apb_inst|comb~0 .coord_z = 12;
defparam \macro_inst|ahb2apb_inst|comb~0 .mask = 16'hCC00;
defparam \macro_inst|ahb2apb_inst|comb~0 .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|comb~0 .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|comb~0 .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|comb~0 .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|comb~0 .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|haddr[15] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_haddr[15] ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|haddr [15]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X51_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X51_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|haddr[15]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|haddr [15]));
defparam \macro_inst|ahb2apb_inst|haddr[15] .coord_x = 14;
defparam \macro_inst|ahb2apb_inst|haddr[15] .coord_y = 5;
defparam \macro_inst|ahb2apb_inst|haddr[15] .coord_z = 2;
defparam \macro_inst|ahb2apb_inst|haddr[15] .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|haddr[15] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[15] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[15] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[15] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[15] .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|hdone (
	.A(vcc),
	.B(\macro_inst|ahb2apb_inst|pvalid~q ),
	.C(vcc),
	.D(\macro_inst|ahb2apb_inst|hreadyout~q ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|hdone~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X52_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X52_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|hdone~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|hdone~q ));
defparam \macro_inst|ahb2apb_inst|hdone .coord_x = 15;
defparam \macro_inst|ahb2apb_inst|hdone .coord_y = 5;
defparam \macro_inst|ahb2apb_inst|hdone .coord_z = 12;
defparam \macro_inst|ahb2apb_inst|hdone .mask = 16'hFC00;
defparam \macro_inst|ahb2apb_inst|hdone .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|hdone .FeedbackMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|hdone .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|hdone .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|hdone .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|hreadyout (
	.A(\macro_inst|ahb2apb_inst|hdone~q ),
	.B(\macro_inst|ahb2apb_inst|pdone~q ),
	.C(vcc),
	.D(\rv32.mem_ahb_htrans[1] ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|hreadyout~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X52_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X52_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|hreadyout~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|hreadyout~q ));
defparam \macro_inst|ahb2apb_inst|hreadyout .coord_x = 15;
defparam \macro_inst|ahb2apb_inst|hreadyout .coord_y = 5;
defparam \macro_inst|ahb2apb_inst|hreadyout .coord_z = 2;
defparam \macro_inst|ahb2apb_inst|hreadyout .mask = 16'h7F70;
defparam \macro_inst|ahb2apb_inst|hreadyout .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|hreadyout .FeedbackMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|hreadyout .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|hreadyout .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|hreadyout .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|hwrite (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwrite ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|hwrite~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X51_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X51_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|hwrite__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|hwrite~q ));
defparam \macro_inst|ahb2apb_inst|hwrite .coord_x = 14;
defparam \macro_inst|ahb2apb_inst|hwrite .coord_y = 5;
defparam \macro_inst|ahb2apb_inst|hwrite .coord_z = 8;
defparam \macro_inst|ahb2apb_inst|hwrite .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|hwrite .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|hwrite .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|hwrite .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|hwrite .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|hwrite .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|paddr[15] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|ahb2apb_inst|haddr [15]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|paddr [15]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ahb2apb_inst|pwrite~0_combout_X51_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X51_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|paddr[15]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|paddr [15]));
defparam \macro_inst|ahb2apb_inst|paddr[15] .coord_x = 14;
defparam \macro_inst|ahb2apb_inst|paddr[15] .coord_y = 5;
defparam \macro_inst|ahb2apb_inst|paddr[15] .coord_z = 12;
defparam \macro_inst|ahb2apb_inst|paddr[15] .mask = 16'hF0F0;
defparam \macro_inst|ahb2apb_inst|paddr[15] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[15] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[15] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[15] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[15] .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|pdone (
	.A(vcc),
	.B(\macro_inst|ahb2apb_inst|penable~q ),
	.C(vcc),
	.D(\macro_inst|ahb2apb_inst|psel~q ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|pdone~q ),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X52_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|pdone~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|pdone~q ));
defparam \macro_inst|ahb2apb_inst|pdone .coord_x = 15;
defparam \macro_inst|ahb2apb_inst|pdone .coord_y = 5;
defparam \macro_inst|ahb2apb_inst|pdone .coord_z = 5;
defparam \macro_inst|ahb2apb_inst|pdone .mask = 16'h0C00;
defparam \macro_inst|ahb2apb_inst|pdone .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|pdone .FeedbackMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|pdone .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|pdone .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|pdone .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|penable (
	.A(\macro_inst|ahb2apb_inst|apbState.apbSetup~q ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|ahb2apb_inst|apbState.apbIdle~q ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|penable~q ),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X52_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|Selector25~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|penable~q ));
defparam \macro_inst|ahb2apb_inst|penable .coord_x = 15;
defparam \macro_inst|ahb2apb_inst|penable .coord_y = 5;
defparam \macro_inst|ahb2apb_inst|penable .coord_z = 4;
defparam \macro_inst|ahb2apb_inst|penable .mask = 16'hAAFA;
defparam \macro_inst|ahb2apb_inst|penable .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|penable .FeedbackMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|penable .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|penable .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|penable .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|prdata[0] (
	.A(),
	.B(),
	.C(\macro_inst|apb_prdata [0]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X56_Y2_SIG ),
	.SyncReset(SyncReset_X56_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y2_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [0]));
defparam \macro_inst|ahb2apb_inst|prdata[0] .coord_x = 14;
defparam \macro_inst|ahb2apb_inst|prdata[0] .coord_y = 8;
defparam \macro_inst|ahb2apb_inst|prdata[0] .coord_z = 13;
defparam \macro_inst|ahb2apb_inst|prdata[0] .mask = 16'hFFFF;
defparam \macro_inst|ahb2apb_inst|prdata[0] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[0] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[0] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[0] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|prdata[1] (
	.A(),
	.B(),
	.C(\macro_inst|apb_prdata [1]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [1]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X56_Y2_SIG ),
	.SyncReset(SyncReset_X56_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y2_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [1]));
defparam \macro_inst|ahb2apb_inst|prdata[1] .coord_x = 14;
defparam \macro_inst|ahb2apb_inst|prdata[1] .coord_y = 8;
defparam \macro_inst|ahb2apb_inst|prdata[1] .coord_z = 6;
defparam \macro_inst|ahb2apb_inst|prdata[1] .mask = 16'hFFFF;
defparam \macro_inst|ahb2apb_inst|prdata[1] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[1] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[1] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[1] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[1] .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|prdata[2] (
	.A(),
	.B(),
	.C(\macro_inst|apb_prdata [2]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [2]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X56_Y2_SIG ),
	.SyncReset(SyncReset_X56_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y2_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [2]));
defparam \macro_inst|ahb2apb_inst|prdata[2] .coord_x = 14;
defparam \macro_inst|ahb2apb_inst|prdata[2] .coord_y = 8;
defparam \macro_inst|ahb2apb_inst|prdata[2] .coord_z = 14;
defparam \macro_inst|ahb2apb_inst|prdata[2] .mask = 16'hFFFF;
defparam \macro_inst|ahb2apb_inst|prdata[2] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[2] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[2] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[2] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[2] .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|prdata[3] (
	.A(),
	.B(),
	.C(\macro_inst|apb_prdata [3]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [3]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X56_Y2_SIG ),
	.SyncReset(SyncReset_X56_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y2_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [3]));
defparam \macro_inst|ahb2apb_inst|prdata[3] .coord_x = 14;
defparam \macro_inst|ahb2apb_inst|prdata[3] .coord_y = 8;
defparam \macro_inst|ahb2apb_inst|prdata[3] .coord_z = 10;
defparam \macro_inst|ahb2apb_inst|prdata[3] .mask = 16'hFFFF;
defparam \macro_inst|ahb2apb_inst|prdata[3] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[3] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[3] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[3] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[3] .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|prdata[4] (
	.A(),
	.B(),
	.C(\macro_inst|apb_prdata [4]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [4]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ahb2apb_inst|comb~0_combout_X53_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X53_Y2_SIG ),
	.SyncReset(SyncReset_X53_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y2_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [4]));
defparam \macro_inst|ahb2apb_inst|prdata[4] .coord_x = 14;
defparam \macro_inst|ahb2apb_inst|prdata[4] .coord_y = 6;
defparam \macro_inst|ahb2apb_inst|prdata[4] .coord_z = 11;
defparam \macro_inst|ahb2apb_inst|prdata[4] .mask = 16'hFFFF;
defparam \macro_inst|ahb2apb_inst|prdata[4] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[4] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[4] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[4] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[4] .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|prdata[5] (
	.A(),
	.B(),
	.C(\macro_inst|apb_prdata [5]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [5]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ahb2apb_inst|comb~0_combout_X53_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X53_Y2_SIG ),
	.SyncReset(SyncReset_X53_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y2_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [5]));
defparam \macro_inst|ahb2apb_inst|prdata[5] .coord_x = 14;
defparam \macro_inst|ahb2apb_inst|prdata[5] .coord_y = 6;
defparam \macro_inst|ahb2apb_inst|prdata[5] .coord_z = 9;
defparam \macro_inst|ahb2apb_inst|prdata[5] .mask = 16'hFFFF;
defparam \macro_inst|ahb2apb_inst|prdata[5] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[5] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[5] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[5] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[5] .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|prdata[6] (
	.A(),
	.B(),
	.C(\macro_inst|apb_prdata [6]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [6]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ahb2apb_inst|comb~0_combout_X53_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X53_Y2_SIG ),
	.SyncReset(SyncReset_X53_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y2_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [6]));
defparam \macro_inst|ahb2apb_inst|prdata[6] .coord_x = 14;
defparam \macro_inst|ahb2apb_inst|prdata[6] .coord_y = 6;
defparam \macro_inst|ahb2apb_inst|prdata[6] .coord_z = 15;
defparam \macro_inst|ahb2apb_inst|prdata[6] .mask = 16'hFFFF;
defparam \macro_inst|ahb2apb_inst|prdata[6] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[6] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[6] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[6] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[6] .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|prdata[7] (
	.A(),
	.B(),
	.C(\macro_inst|apb_prdata [7]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [7]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ahb2apb_inst|comb~0_combout_X53_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X53_Y2_SIG ),
	.SyncReset(SyncReset_X53_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y2_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [7]));
defparam \macro_inst|ahb2apb_inst|prdata[7] .coord_x = 14;
defparam \macro_inst|ahb2apb_inst|prdata[7] .coord_y = 6;
defparam \macro_inst|ahb2apb_inst|prdata[7] .coord_z = 5;
defparam \macro_inst|ahb2apb_inst|prdata[7] .mask = 16'hFFFF;
defparam \macro_inst|ahb2apb_inst|prdata[7] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[7] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[7] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[7] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[7] .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|prdata[8] (
	.A(),
	.B(),
	.C(\macro_inst|apb_prdata [8]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [8]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X56_Y2_SIG ),
	.SyncReset(SyncReset_X56_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y2_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [8]));
defparam \macro_inst|ahb2apb_inst|prdata[8] .coord_x = 14;
defparam \macro_inst|ahb2apb_inst|prdata[8] .coord_y = 8;
defparam \macro_inst|ahb2apb_inst|prdata[8] .coord_z = 0;
defparam \macro_inst|ahb2apb_inst|prdata[8] .mask = 16'hFFFF;
defparam \macro_inst|ahb2apb_inst|prdata[8] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[8] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[8] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[8] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[8] .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|prdata[9] (
	.A(),
	.B(),
	.C(\macro_inst|apb_prdata [9]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [9]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X56_Y2_SIG ),
	.SyncReset(SyncReset_X56_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y2_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [9]));
defparam \macro_inst|ahb2apb_inst|prdata[9] .coord_x = 14;
defparam \macro_inst|ahb2apb_inst|prdata[9] .coord_y = 8;
defparam \macro_inst|ahb2apb_inst|prdata[9] .coord_z = 7;
defparam \macro_inst|ahb2apb_inst|prdata[9] .mask = 16'hFFFF;
defparam \macro_inst|ahb2apb_inst|prdata[9] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[9] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[9] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[9] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[9] .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|psel (
	.A(\macro_inst|ahb2apb_inst|apbState.apbSetup~q ),
	.B(\macro_inst|ahb2apb_inst|apbState.apbIdle~q ),
	.C(vcc),
	.D(\macro_inst|ahb2apb_inst|pvalid~q ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|psel~q ),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X52_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|psel~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|psel~q ));
defparam \macro_inst|ahb2apb_inst|psel .coord_x = 15;
defparam \macro_inst|ahb2apb_inst|psel .coord_y = 5;
defparam \macro_inst|ahb2apb_inst|psel .coord_z = 13;
defparam \macro_inst|ahb2apb_inst|psel .mask = 16'hF7B0;
defparam \macro_inst|ahb2apb_inst|psel .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|psel .FeedbackMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|psel .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|psel .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|psel .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|pvalid (
	.A(vcc),
	.B(\macro_inst|ahb2apb_inst|pdone~q ),
	.C(\macro_inst|ahb2apb_inst|hreadyout~q ),
	.D(\macro_inst|ahb2apb_inst|psel~q ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|pvalid~q ),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X52_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|always2~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|pvalid~q ));
defparam \macro_inst|ahb2apb_inst|pvalid .coord_x = 15;
defparam \macro_inst|ahb2apb_inst|pvalid .coord_y = 5;
defparam \macro_inst|ahb2apb_inst|pvalid .coord_z = 1;
defparam \macro_inst|ahb2apb_inst|pvalid .mask = 16'h0030;
defparam \macro_inst|ahb2apb_inst|pvalid .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|pvalid .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|pvalid .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|pvalid .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|pvalid .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|pwrite (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|ahb2apb_inst|hwrite~q ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|pwrite~q ),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ahb2apb_inst|pwrite~0_combout_X51_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~combout__AsyncReset_X51_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|pwrite~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|pwrite~q ));
defparam \macro_inst|ahb2apb_inst|pwrite .coord_x = 14;
defparam \macro_inst|ahb2apb_inst|pwrite .coord_y = 5;
defparam \macro_inst|ahb2apb_inst|pwrite .coord_z = 6;
defparam \macro_inst|ahb2apb_inst|pwrite .mask = 16'hF0F0;
defparam \macro_inst|ahb2apb_inst|pwrite .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|pwrite .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|pwrite .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|pwrite .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|pwrite .CarryEnb = 1'b1;

alta_slice \macro_inst|ahb2apb_inst|pwrite~0 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|ahb2apb_inst|apbState.apbSetup~q ),
	.D(\macro_inst|ahb2apb_inst|pvalid~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|pwrite~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|ahb2apb_inst|pwrite~0 .coord_x = 15;
defparam \macro_inst|ahb2apb_inst|pwrite~0 .coord_y = 5;
defparam \macro_inst|ahb2apb_inst|pwrite~0 .coord_z = 15;
defparam \macro_inst|ahb2apb_inst|pwrite~0 .mask = 16'h0F00;
defparam \macro_inst|ahb2apb_inst|pwrite~0 .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|pwrite~0 .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|pwrite~0 .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|pwrite~0 .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|pwrite~0 .CarryEnb = 1'b1;

alta_slice \macro_inst|always5~0 (
	.A(\macro_inst|ahb2apb_inst|paddr [15]),
	.B(\macro_inst|ahb2apb_inst|pwrite~q ),
	.C(\macro_inst|ahb2apb_inst|penable~q ),
	.D(\macro_inst|ahb2apb_inst|psel~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|always5~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|always5~0 .coord_x = 15;
defparam \macro_inst|always5~0 .coord_y = 5;
defparam \macro_inst|always5~0 .coord_z = 8;
defparam \macro_inst|always5~0 .mask = 16'h0100;
defparam \macro_inst|always5~0 .modeMux = 1'b0;
defparam \macro_inst|always5~0 .FeedbackMux = 1'b0;
defparam \macro_inst|always5~0 .ShiftMux = 1'b0;
defparam \macro_inst|always5~0 .BypassEn = 1'b0;
defparam \macro_inst|always5~0 .CarryEnb = 1'b1;

alta_slice \macro_inst|apb_prdata[0] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [9]),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [0]),
	.D(\macro_inst|always5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|apb_prdata [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ren~0_combout_X56_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata~0_combout ),
	.Cout(),
	.Q(\macro_inst|apb_prdata [0]));
defparam \macro_inst|apb_prdata[0] .coord_x = 14;
defparam \macro_inst|apb_prdata[0] .coord_y = 8;
defparam \macro_inst|apb_prdata[0] .coord_z = 4;
defparam \macro_inst|apb_prdata[0] .mask = 16'hCCF0;
defparam \macro_inst|apb_prdata[0] .modeMux = 1'b0;
defparam \macro_inst|apb_prdata[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_prdata[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_prdata[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_prdata[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|apb_prdata[1] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [1]),
	.B(vcc),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [10]),
	.D(\macro_inst|always5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|apb_prdata [1]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ren~0_combout_X56_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata~1_combout ),
	.Cout(),
	.Q(\macro_inst|apb_prdata [1]));
defparam \macro_inst|apb_prdata[1] .coord_x = 14;
defparam \macro_inst|apb_prdata[1] .coord_y = 8;
defparam \macro_inst|apb_prdata[1] .coord_z = 2;
defparam \macro_inst|apb_prdata[1] .mask = 16'hF0AA;
defparam \macro_inst|apb_prdata[1] .modeMux = 1'b0;
defparam \macro_inst|apb_prdata[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_prdata[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_prdata[1] .BypassEn = 1'b0;
defparam \macro_inst|apb_prdata[1] .CarryEnb = 1'b1;

alta_slice \macro_inst|apb_prdata[2] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [11]),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [2]),
	.D(\macro_inst|always5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|apb_prdata [2]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ren~0_combout_X56_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata~2_combout ),
	.Cout(),
	.Q(\macro_inst|apb_prdata [2]));
defparam \macro_inst|apb_prdata[2] .coord_x = 14;
defparam \macro_inst|apb_prdata[2] .coord_y = 8;
defparam \macro_inst|apb_prdata[2] .coord_z = 15;
defparam \macro_inst|apb_prdata[2] .mask = 16'hCCF0;
defparam \macro_inst|apb_prdata[2] .modeMux = 1'b0;
defparam \macro_inst|apb_prdata[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_prdata[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_prdata[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_prdata[2] .CarryEnb = 1'b1;

alta_slice \macro_inst|apb_prdata[3] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [12]),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [3]),
	.D(\macro_inst|always5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|apb_prdata [3]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ren~0_combout_X56_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata~3_combout ),
	.Cout(),
	.Q(\macro_inst|apb_prdata [3]));
defparam \macro_inst|apb_prdata[3] .coord_x = 14;
defparam \macro_inst|apb_prdata[3] .coord_y = 8;
defparam \macro_inst|apb_prdata[3] .coord_z = 11;
defparam \macro_inst|apb_prdata[3] .mask = 16'hCCF0;
defparam \macro_inst|apb_prdata[3] .modeMux = 1'b0;
defparam \macro_inst|apb_prdata[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_prdata[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_prdata[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_prdata[3] .CarryEnb = 1'b1;

alta_slice \macro_inst|apb_prdata[4] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [4]),
	.B(vcc),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [13]),
	.D(\macro_inst|always5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|apb_prdata [4]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ren~0_combout_X53_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X53_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata~4_combout ),
	.Cout(),
	.Q(\macro_inst|apb_prdata [4]));
defparam \macro_inst|apb_prdata[4] .coord_x = 14;
defparam \macro_inst|apb_prdata[4] .coord_y = 6;
defparam \macro_inst|apb_prdata[4] .coord_z = 10;
defparam \macro_inst|apb_prdata[4] .mask = 16'hF0AA;
defparam \macro_inst|apb_prdata[4] .modeMux = 1'b0;
defparam \macro_inst|apb_prdata[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_prdata[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_prdata[4] .BypassEn = 1'b0;
defparam \macro_inst|apb_prdata[4] .CarryEnb = 1'b1;

alta_slice \macro_inst|apb_prdata[5] (
	.A(vcc),
	.B(\macro_inst|always5~0_combout ),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [14]),
	.D(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [5]),
	.Cin(),
	.Qin(\macro_inst|apb_prdata [5]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ren~0_combout_X53_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X53_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata~5_combout ),
	.Cout(),
	.Q(\macro_inst|apb_prdata [5]));
defparam \macro_inst|apb_prdata[5] .coord_x = 14;
defparam \macro_inst|apb_prdata[5] .coord_y = 6;
defparam \macro_inst|apb_prdata[5] .coord_z = 2;
defparam \macro_inst|apb_prdata[5] .mask = 16'hF3C0;
defparam \macro_inst|apb_prdata[5] .modeMux = 1'b0;
defparam \macro_inst|apb_prdata[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_prdata[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_prdata[5] .BypassEn = 1'b0;
defparam \macro_inst|apb_prdata[5] .CarryEnb = 1'b1;

alta_slice \macro_inst|apb_prdata[6] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [15]),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [6]),
	.D(\macro_inst|always5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|apb_prdata [6]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ren~0_combout_X53_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X53_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata~6_combout ),
	.Cout(),
	.Q(\macro_inst|apb_prdata [6]));
defparam \macro_inst|apb_prdata[6] .coord_x = 14;
defparam \macro_inst|apb_prdata[6] .coord_y = 6;
defparam \macro_inst|apb_prdata[6] .coord_z = 14;
defparam \macro_inst|apb_prdata[6] .mask = 16'hCCF0;
defparam \macro_inst|apb_prdata[6] .modeMux = 1'b0;
defparam \macro_inst|apb_prdata[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_prdata[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_prdata[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_prdata[6] .CarryEnb = 1'b1;

alta_slice \macro_inst|apb_prdata[7] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [16]),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [7]),
	.D(\macro_inst|always5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|apb_prdata [7]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ren~0_combout_X53_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X53_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata~7_combout ),
	.Cout(),
	.Q(\macro_inst|apb_prdata [7]));
defparam \macro_inst|apb_prdata[7] .coord_x = 14;
defparam \macro_inst|apb_prdata[7] .coord_y = 6;
defparam \macro_inst|apb_prdata[7] .coord_z = 4;
defparam \macro_inst|apb_prdata[7] .mask = 16'hCCF0;
defparam \macro_inst|apb_prdata[7] .modeMux = 1'b0;
defparam \macro_inst|apb_prdata[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_prdata[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_prdata[7] .BypassEn = 1'b0;
defparam \macro_inst|apb_prdata[7] .CarryEnb = 1'b1;

alta_slice \macro_inst|apb_prdata[8] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [8]),
	.D(\macro_inst|always5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|apb_prdata [8]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ren~0_combout_X56_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata~8_combout ),
	.Cout(),
	.Q(\macro_inst|apb_prdata [8]));
defparam \macro_inst|apb_prdata[8] .coord_x = 14;
defparam \macro_inst|apb_prdata[8] .coord_y = 8;
defparam \macro_inst|apb_prdata[8] .coord_z = 1;
defparam \macro_inst|apb_prdata[8] .mask = 16'h00F0;
defparam \macro_inst|apb_prdata[8] .modeMux = 1'b0;
defparam \macro_inst|apb_prdata[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_prdata[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_prdata[8] .BypassEn = 1'b0;
defparam \macro_inst|apb_prdata[8] .CarryEnb = 1'b1;

alta_slice \macro_inst|apb_prdata[9] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [9]),
	.C(vcc),
	.D(\macro_inst|always5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|apb_prdata [9]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|ren~0_combout_X56_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata~9_combout ),
	.Cout(),
	.Q(\macro_inst|apb_prdata [9]));
defparam \macro_inst|apb_prdata[9] .coord_x = 14;
defparam \macro_inst|apb_prdata[9] .coord_y = 8;
defparam \macro_inst|apb_prdata[9] .coord_z = 12;
defparam \macro_inst|apb_prdata[9] .mask = 16'h00CC;
defparam \macro_inst|apb_prdata[9] .modeMux = 1'b0;
defparam \macro_inst|apb_prdata[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_prdata[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_prdata[9] .BypassEn = 1'b0;
defparam \macro_inst|apb_prdata[9] .CarryEnb = 1'b1;

alta_slice \macro_inst|apb_pwdata_r[0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[0] ),
	.Cin(),
	.Qin(\macro_inst|apb_pwdata_r [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X56_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X56_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_pwdata_r[0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|apb_pwdata_r [0]));
defparam \macro_inst|apb_pwdata_r[0] .coord_x = 14;
defparam \macro_inst|apb_pwdata_r[0] .coord_y = 7;
defparam \macro_inst|apb_pwdata_r[0] .coord_z = 3;
defparam \macro_inst|apb_pwdata_r[0] .mask = 16'hFF00;
defparam \macro_inst|apb_pwdata_r[0] .modeMux = 1'b1;
defparam \macro_inst|apb_pwdata_r[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_pwdata_r[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_pwdata_r[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_pwdata_r[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|apb_pwdata_r[1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|apb_pwdata_r [1]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X56_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X56_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_pwdata_r[1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|apb_pwdata_r [1]));
defparam \macro_inst|apb_pwdata_r[1] .coord_x = 14;
defparam \macro_inst|apb_pwdata_r[1] .coord_y = 7;
defparam \macro_inst|apb_pwdata_r[1] .coord_z = 2;
defparam \macro_inst|apb_pwdata_r[1] .mask = 16'hFF00;
defparam \macro_inst|apb_pwdata_r[1] .modeMux = 1'b1;
defparam \macro_inst|apb_pwdata_r[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_pwdata_r[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_pwdata_r[1] .BypassEn = 1'b0;
defparam \macro_inst|apb_pwdata_r[1] .CarryEnb = 1'b1;

alta_slice \macro_inst|apb_pwdata_r[2] (
	.A(),
	.B(),
	.C(\rv32.mem_ahb_hwdata[2] ),
	.D(),
	.Cin(),
	.Qin(\macro_inst|apb_pwdata_r [2]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X56_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X56_Y1_GND),
	.SyncReset(SyncReset_X56_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y1_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|apb_pwdata_r [2]));
defparam \macro_inst|apb_pwdata_r[2] .coord_x = 14;
defparam \macro_inst|apb_pwdata_r[2] .coord_y = 7;
defparam \macro_inst|apb_pwdata_r[2] .coord_z = 5;
defparam \macro_inst|apb_pwdata_r[2] .mask = 16'hFFFF;
defparam \macro_inst|apb_pwdata_r[2] .modeMux = 1'b1;
defparam \macro_inst|apb_pwdata_r[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_pwdata_r[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_pwdata_r[2] .BypassEn = 1'b1;
defparam \macro_inst|apb_pwdata_r[2] .CarryEnb = 1'b1;

alta_slice \macro_inst|apb_pwdata_r[3] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[3] ),
	.Cin(),
	.Qin(\macro_inst|apb_pwdata_r [3]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X56_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X56_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_pwdata_r[3]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|apb_pwdata_r [3]));
defparam \macro_inst|apb_pwdata_r[3] .coord_x = 14;
defparam \macro_inst|apb_pwdata_r[3] .coord_y = 7;
defparam \macro_inst|apb_pwdata_r[3] .coord_z = 4;
defparam \macro_inst|apb_pwdata_r[3] .mask = 16'hFF00;
defparam \macro_inst|apb_pwdata_r[3] .modeMux = 1'b1;
defparam \macro_inst|apb_pwdata_r[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_pwdata_r[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_pwdata_r[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_pwdata_r[3] .CarryEnb = 1'b1;

alta_slice \macro_inst|apb_pwdata_r[4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[4] ),
	.Cin(),
	.Qin(\macro_inst|apb_pwdata_r [4]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X54_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X54_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_pwdata_r[4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|apb_pwdata_r [4]));
defparam \macro_inst|apb_pwdata_r[4] .coord_x = 14;
defparam \macro_inst|apb_pwdata_r[4] .coord_y = 3;
defparam \macro_inst|apb_pwdata_r[4] .coord_z = 2;
defparam \macro_inst|apb_pwdata_r[4] .mask = 16'hFF00;
defparam \macro_inst|apb_pwdata_r[4] .modeMux = 1'b1;
defparam \macro_inst|apb_pwdata_r[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_pwdata_r[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_pwdata_r[4] .BypassEn = 1'b0;
defparam \macro_inst|apb_pwdata_r[4] .CarryEnb = 1'b1;

alta_slice \macro_inst|apb_pwdata_r[5] (
	.A(\macro_inst|spi_inst|tx_data_r [3]),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [13]),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(\macro_inst|tx_en [0]),
	.Cin(),
	.Qin(\macro_inst|apb_pwdata_r [5]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X54_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X54_Y1_GND),
	.SyncReset(SyncReset_X54_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X54_Y1_VCC),
	.LutOut(\macro_inst|spi_inst|tx_data_r~4_combout ),
	.Cout(),
	.Q(\macro_inst|apb_pwdata_r [5]));
defparam \macro_inst|apb_pwdata_r[5] .coord_x = 14;
defparam \macro_inst|apb_pwdata_r[5] .coord_y = 4;
defparam \macro_inst|apb_pwdata_r[5] .coord_z = 11;
defparam \macro_inst|apb_pwdata_r[5] .mask = 16'h33AA;
defparam \macro_inst|apb_pwdata_r[5] .modeMux = 1'b0;
defparam \macro_inst|apb_pwdata_r[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_pwdata_r[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_pwdata_r[5] .BypassEn = 1'b1;
defparam \macro_inst|apb_pwdata_r[5] .CarryEnb = 1'b1;

alta_slice \macro_inst|apb_pwdata_r[6] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[6] ),
	.Cin(),
	.Qin(\macro_inst|apb_pwdata_r [6]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X54_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X54_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_pwdata_r[6]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|apb_pwdata_r [6]));
defparam \macro_inst|apb_pwdata_r[6] .coord_x = 14;
defparam \macro_inst|apb_pwdata_r[6] .coord_y = 3;
defparam \macro_inst|apb_pwdata_r[6] .coord_z = 0;
defparam \macro_inst|apb_pwdata_r[6] .mask = 16'hFF00;
defparam \macro_inst|apb_pwdata_r[6] .modeMux = 1'b1;
defparam \macro_inst|apb_pwdata_r[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_pwdata_r[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_pwdata_r[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_pwdata_r[6] .CarryEnb = 1'b1;

alta_slice \macro_inst|apb_pwdata_r[7] (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [10]),
	.B(\macro_inst|spi_inst|tx_data_r [0]),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(\macro_inst|tx_en [0]),
	.Cin(),
	.Qin(\macro_inst|apb_pwdata_r [7]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X54_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X54_Y1_GND),
	.SyncReset(SyncReset_X54_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X54_Y1_VCC),
	.LutOut(\macro_inst|spi_inst|tx_data_r~7_combout ),
	.Cout(),
	.Q(\macro_inst|apb_pwdata_r [7]));
defparam \macro_inst|apb_pwdata_r[7] .coord_x = 14;
defparam \macro_inst|apb_pwdata_r[7] .coord_y = 4;
defparam \macro_inst|apb_pwdata_r[7] .coord_z = 15;
defparam \macro_inst|apb_pwdata_r[7] .mask = 16'h55CC;
defparam \macro_inst|apb_pwdata_r[7] .modeMux = 1'b0;
defparam \macro_inst|apb_pwdata_r[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_pwdata_r[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_pwdata_r[7] .BypassEn = 1'b1;
defparam \macro_inst|apb_pwdata_r[7] .CarryEnb = 1'b1;

alta_slice \macro_inst|csen[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|tx_fifo_empty_r [2]),
	.Cin(),
	.Qin(\macro_inst|csen [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X50_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X50_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|csen[0]~0_combout ),
	.Cout(),
	.Q(\macro_inst|csen [0]));
defparam \macro_inst|csen[0] .coord_x = 14;
defparam \macro_inst|csen[0] .coord_y = 2;
defparam \macro_inst|csen[0] .coord_z = 13;
defparam \macro_inst|csen[0] .mask = 16'h00FF;
defparam \macro_inst|csen[0] .modeMux = 1'b0;
defparam \macro_inst|csen[0] .FeedbackMux = 1'b0;
defparam \macro_inst|csen[0] .ShiftMux = 1'b0;
defparam \macro_inst|csen[0] .BypassEn = 1'b0;
defparam \macro_inst|csen[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|ren~0 (
	.A(vcc),
	.B(\macro_inst|ahb2apb_inst|pwrite~q ),
	.C(\macro_inst|ahb2apb_inst|penable~q ),
	.D(\macro_inst|ahb2apb_inst|psel~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ren~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|ren~0 .coord_x = 15;
defparam \macro_inst|ren~0 .coord_y = 5;
defparam \macro_inst|ren~0 .coord_z = 6;
defparam \macro_inst|ren~0 .mask = 16'h0300;
defparam \macro_inst|ren~0 .modeMux = 1'b0;
defparam \macro_inst|ren~0 .FeedbackMux = 1'b0;
defparam \macro_inst|ren~0 .ShiftMux = 1'b0;
defparam \macro_inst|ren~0 .BypassEn = 1'b0;
defparam \macro_inst|ren~0 .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_data[0] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|spi_inst|rx_data [0]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_data [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_data[0]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_data [0]));
defparam \macro_inst|rx_fifo_data[0] .coord_x = 16;
defparam \macro_inst|rx_fifo_data[0] .coord_y = 3;
defparam \macro_inst|rx_fifo_data[0] .coord_z = 8;
defparam \macro_inst|rx_fifo_data[0] .mask = 16'hF0F0;
defparam \macro_inst|rx_fifo_data[0] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_data[0] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_data[0] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_data[0] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_data[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_data[1] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|spi_inst|rx_data [1]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_data [1]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_data[1]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_data [1]));
defparam \macro_inst|rx_fifo_data[1] .coord_x = 16;
defparam \macro_inst|rx_fifo_data[1] .coord_y = 3;
defparam \macro_inst|rx_fifo_data[1] .coord_z = 13;
defparam \macro_inst|rx_fifo_data[1] .mask = 16'hF0F0;
defparam \macro_inst|rx_fifo_data[1] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_data[1] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_data[1] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_data[1] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_data[1] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_data[2] (
	.A(\macro_inst|spi_inst|sck~q ),
	.B(vcc),
	.C(\macro_inst|spi_inst|rx_data [2]),
	.D(\macro_inst|spi_inst|sck_cnt_bit0 [0]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_data [2]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(SyncReset_X52_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X52_Y1_VCC),
	.LutOut(\macro_inst|spi_inst|always7~0_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_data [2]));
defparam \macro_inst|rx_fifo_data[2] .coord_x = 16;
defparam \macro_inst|rx_fifo_data[2] .coord_y = 3;
defparam \macro_inst|rx_fifo_data[2] .coord_z = 15;
defparam \macro_inst|rx_fifo_data[2] .mask = 16'h5500;
defparam \macro_inst|rx_fifo_data[2] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_data[2] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_data[2] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_data[2] .BypassEn = 1'b1;
defparam \macro_inst|rx_fifo_data[2] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_data[3] (
	.A(),
	.B(),
	.C(\macro_inst|spi_inst|rx_data [3]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_data [3]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(SyncReset_X52_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X52_Y1_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|rx_fifo_data [3]));
defparam \macro_inst|rx_fifo_data[3] .coord_x = 16;
defparam \macro_inst|rx_fifo_data[3] .coord_y = 3;
defparam \macro_inst|rx_fifo_data[3] .coord_z = 11;
defparam \macro_inst|rx_fifo_data[3] .mask = 16'hFFFF;
defparam \macro_inst|rx_fifo_data[3] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_data[3] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_data[3] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_data[3] .BypassEn = 1'b1;
defparam \macro_inst|rx_fifo_data[3] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_data[4] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|spi_inst|rx_data [4]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_data [4]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X54_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X54_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_data[4]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_data [4]));
defparam \macro_inst|rx_fifo_data[4] .coord_x = 14;
defparam \macro_inst|rx_fifo_data[4] .coord_y = 3;
defparam \macro_inst|rx_fifo_data[4] .coord_z = 13;
defparam \macro_inst|rx_fifo_data[4] .mask = 16'hF0F0;
defparam \macro_inst|rx_fifo_data[4] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_data[4] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_data[4] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_data[4] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_data[4] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_data[5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|spi_inst|rx_data [5]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_data [5]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_data[5]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_data [5]));
defparam \macro_inst|rx_fifo_data[5] .coord_x = 16;
defparam \macro_inst|rx_fifo_data[5] .coord_y = 3;
defparam \macro_inst|rx_fifo_data[5] .coord_z = 12;
defparam \macro_inst|rx_fifo_data[5] .mask = 16'hFF00;
defparam \macro_inst|rx_fifo_data[5] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_data[5] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_data[5] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_data[5] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_data[5] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_data[6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|spi_inst|rx_data [6]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_data [6]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_data[6]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_data [6]));
defparam \macro_inst|rx_fifo_data[6] .coord_x = 16;
defparam \macro_inst|rx_fifo_data[6] .coord_y = 3;
defparam \macro_inst|rx_fifo_data[6] .coord_z = 0;
defparam \macro_inst|rx_fifo_data[6] .mask = 16'hFF00;
defparam \macro_inst|rx_fifo_data[6] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_data[6] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_data[6] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_data[6] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_data[6] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_data[7] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|spi_inst|rx_data [7]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_data [7]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_data[7]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_data [7]));
defparam \macro_inst|rx_fifo_data[7] .coord_x = 16;
defparam \macro_inst|rx_fifo_data[7] .coord_y = 3;
defparam \macro_inst|rx_fifo_data[7] .coord_z = 5;
defparam \macro_inst|rx_fifo_data[7] .mask = 16'hFF00;
defparam \macro_inst|rx_fifo_data[7] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_data[7] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_data[7] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_data[7] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_data[7] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_data_r[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|rx_fifo_data [0]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_data_r [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_data_r[0]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_data_r [0]));
defparam \macro_inst|rx_fifo_data_r[0] .coord_x = 16;
defparam \macro_inst|rx_fifo_data_r[0] .coord_y = 3;
defparam \macro_inst|rx_fifo_data_r[0] .coord_z = 9;
defparam \macro_inst|rx_fifo_data_r[0] .mask = 16'hFF00;
defparam \macro_inst|rx_fifo_data_r[0] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[0] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[0] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[0] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_data_r[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_data_r[1] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|rx_fifo_data [1]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_data_r [1]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_data_r[1]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_data_r [1]));
defparam \macro_inst|rx_fifo_data_r[1] .coord_x = 16;
defparam \macro_inst|rx_fifo_data_r[1] .coord_y = 3;
defparam \macro_inst|rx_fifo_data_r[1] .coord_z = 7;
defparam \macro_inst|rx_fifo_data_r[1] .mask = 16'hFF00;
defparam \macro_inst|rx_fifo_data_r[1] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[1] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[1] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[1] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_data_r[1] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_data_r[2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|rx_fifo_data [2]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_data_r [2]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_data_r[2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_data_r [2]));
defparam \macro_inst|rx_fifo_data_r[2] .coord_x = 16;
defparam \macro_inst|rx_fifo_data_r[2] .coord_y = 3;
defparam \macro_inst|rx_fifo_data_r[2] .coord_z = 3;
defparam \macro_inst|rx_fifo_data_r[2] .mask = 16'hFF00;
defparam \macro_inst|rx_fifo_data_r[2] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[2] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[2] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[2] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_data_r[2] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_data_r[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|rx_fifo_data [3]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_data_r [3]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_data_r[3]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_data_r [3]));
defparam \macro_inst|rx_fifo_data_r[3] .coord_x = 16;
defparam \macro_inst|rx_fifo_data_r[3] .coord_y = 3;
defparam \macro_inst|rx_fifo_data_r[3] .coord_z = 10;
defparam \macro_inst|rx_fifo_data_r[3] .mask = 16'hFF00;
defparam \macro_inst|rx_fifo_data_r[3] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[3] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[3] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[3] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_data_r[3] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_data_r[4] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|rx_fifo_data [4]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_data_r [4]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X54_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X54_Y2_GND),
	.SyncReset(SyncReset_X54_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X54_Y2_VCC),
	.LutOut(mem_ahb_hrdata[23]),
	.Cout(),
	.Q(\macro_inst|rx_fifo_data_r [4]));
defparam \macro_inst|rx_fifo_data_r[4] .coord_x = 14;
defparam \macro_inst|rx_fifo_data_r[4] .coord_y = 3;
defparam \macro_inst|rx_fifo_data_r[4] .coord_z = 1;
defparam \macro_inst|rx_fifo_data_r[4] .mask = 16'h0000;
defparam \macro_inst|rx_fifo_data_r[4] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[4] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[4] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[4] .BypassEn = 1'b1;
defparam \macro_inst|rx_fifo_data_r[4] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_data_r[5] (
	.A(),
	.B(),
	.C(\macro_inst|rx_fifo_data [5]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_data_r [5]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(SyncReset_X52_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X52_Y1_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|rx_fifo_data_r [5]));
defparam \macro_inst|rx_fifo_data_r[5] .coord_x = 16;
defparam \macro_inst|rx_fifo_data_r[5] .coord_y = 3;
defparam \macro_inst|rx_fifo_data_r[5] .coord_z = 2;
defparam \macro_inst|rx_fifo_data_r[5] .mask = 16'hFFFF;
defparam \macro_inst|rx_fifo_data_r[5] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_data_r[5] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[5] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[5] .BypassEn = 1'b1;
defparam \macro_inst|rx_fifo_data_r[5] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_data_r[6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|rx_fifo_data [6]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_data_r [6]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_data_r[6]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_data_r [6]));
defparam \macro_inst|rx_fifo_data_r[6] .coord_x = 16;
defparam \macro_inst|rx_fifo_data_r[6] .coord_y = 3;
defparam \macro_inst|rx_fifo_data_r[6] .coord_z = 1;
defparam \macro_inst|rx_fifo_data_r[6] .mask = 16'hFF00;
defparam \macro_inst|rx_fifo_data_r[6] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[6] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[6] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[6] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_data_r[6] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_data_r[7] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|rx_fifo_data [7]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_data_r [7]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_data_r[7]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_data_r [7]));
defparam \macro_inst|rx_fifo_data_r[7] .coord_x = 16;
defparam \macro_inst|rx_fifo_data_r[7] .coord_y = 3;
defparam \macro_inst|rx_fifo_data_r[7] .coord_z = 6;
defparam \macro_inst|rx_fifo_data_r[7] .mask = 16'hFF00;
defparam \macro_inst|rx_fifo_data_r[7] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[7] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[7] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_data_r[7] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_data_r[7] .CarryEnb = 1'b1;

alta_bram9k \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 (
	.DataInA({vcc, \macro_inst|rx_fifo_data_r [7], \macro_inst|rx_fifo_data_r [6], \macro_inst|rx_fifo_data_r [5], \macro_inst|rx_fifo_data_r [4], \macro_inst|rx_fifo_data_r [3], \macro_inst|rx_fifo_data_r [2], \macro_inst|rx_fifo_data_r [1], \macro_inst|rx_fifo_data_r [0], vcc, \macro_inst|rx_fifo_data_r [7], \macro_inst|rx_fifo_data_r [6], \macro_inst|rx_fifo_data_r [5], \macro_inst|rx_fifo_data_r [4], \macro_inst|rx_fifo_data_r [3], \macro_inst|rx_fifo_data_r [2], \macro_inst|rx_fifo_data_r [1], \macro_inst|rx_fifo_data_r [0]}),
	.DataInB({1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz}),
	.AddressA({\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0], vcc, vcc, vcc}),
	.AddressB({\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[9]~9_combout , \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[8]~8_combout , \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[7]~7_combout , \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[6]~6_combout , \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[5]~5_combout , \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[4]~4_combout , \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[3]~3_combout , \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[2]~2_combout , \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[1]~1_combout , \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[0]~0_combout , vcc, vcc, vcc}),
	.ByteEnA({vcc, vcc}),
	.ByteEnB({1'bz, 1'bz}),
	.DataOutA({\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [17], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [16], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [15], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [14], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [13], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [12], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [11], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [10], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [9], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [8], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [7], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [6], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [5], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [4], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [3], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [2], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [1], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutA [0]}),
	.DataOutB({\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [17], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [16], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [15], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [14], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [13], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [12], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [11], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [10], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [9], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [8], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [7], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [6], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [5], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [4], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [3], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [2], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [1], \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0__DataOutB [0]}),
	.Clk0(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn0(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.AsyncReset0(gnd),
	.Clk1(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn1(),
	.AsyncReset1(gnd),
	.WeA(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.ReA(gnd),
	.WeB(gnd),
	.ReB(vcc),
	.AddressStallA(gnd),
	.AddressStallB(gnd));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .coord_x = 13;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .coord_z = 0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .CLKMODE = 2'b10;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .PACKEDMODE = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .PORTA_CLKIN_EN = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .PORTA_CLKOUT_EN = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .PORTB_CLKIN_EN = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .PORTB_CLKOUT_EN = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .PORTA_RSTIN_EN = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .PORTA_RSTOUT_EN = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .PORTB_RSTIN_EN = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .PORTB_RSTOUT_EN = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .PORTA_WIDTH = 5'b01000;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .PORTB_WIDTH = 5'b01000;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .PORTA_WRITETHRU = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .PORTB_WRITETHRU = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .PORTA_OUTREG = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .PORTB_OUTREG = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .RSEN_DLY = 2'b00;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .DLYTIME = 2'b00;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0 .INIT_VAL = 9216'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~11 (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [0]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [1]),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [8]),
	.D(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~11_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~11 .coord_x = 14;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~11 .coord_y = 8;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~11 .coord_z = 5;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~11 .mask = 16'h0008;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~11 .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~11 .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~11 .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~11 .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~11 .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~12 (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [7]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [4]),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [6]),
	.D(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~12_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~12 .coord_x = 14;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~12 .coord_y = 6;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~12 .coord_z = 7;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~12 .mask = 16'h0001;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~12 .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~12 .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~12 .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~12 .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~12 .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2 (
	.A(\macro_inst|rx_fifo_wen_r [0]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|full_dff~q ),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff~q ),
	.D(\macro_inst|rx_fifo_req [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2 .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2 .coord_y = 6;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2 .coord_z = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2 .mask = 16'hD222;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2 .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2 .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2 .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2 .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2 .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~4 (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [1]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [8]),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [0]),
	.D(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~4 .coord_x = 14;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~4 .coord_y = 8;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~4 .coord_z = 8;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~4 .mask = 16'h8000;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~4 .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~4 .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~4 .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~4 .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~4 .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~5 (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [7]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [4]),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [6]),
	.D(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~5 .coord_x = 14;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~5 .coord_y = 6;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~5 .coord_z = 13;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~5 .mask = 16'h8000;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~5 .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~5 .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~5 .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~5 .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~5 .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~6 (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~4_combout ),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [2]),
	.D(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~5_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~6 .coord_x = 14;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~6 .coord_y = 8;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~6 .coord_z = 9;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~6 .mask = 16'h4000;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~6 .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~6 .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~6 .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~6 .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~6 .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~8_combout ),
	.B(\macro_inst|rx_fifo_wen_r [0]),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|full_dff~q ),
	.D(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_1~0_combout ),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff~q ),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X58_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~14_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff~q ));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff .coord_z = 10;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff .mask = 16'hA2AA;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|full_dff (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~3_combout ),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [3]),
	.D(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~6_combout ),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|full_dff~q ),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X57_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~7_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|full_dff~q ));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|full_dff .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|full_dff .coord_y = 6;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|full_dff .coord_z = 1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|full_dff .mask = 16'hEAAA;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|full_dff .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|full_dff .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|full_dff .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|full_dff .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|full_dff .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[0] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff~q ),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_lsb~q ),
	.C(vcc),
	.D(\macro_inst|rx_fifo_req [0]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X58_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[0]~0_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [0]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[0] .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[0] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[0] .coord_z = 6;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[0] .mask = 16'h72F0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[0] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[0] .FeedbackMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[0] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[0] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[1] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [0]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff~q ),
	.C(vcc),
	.D(\macro_inst|rx_fifo_req [0]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [1]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X59_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X59_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[1]~1_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [1]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[1] .coord_x = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[1] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[1] .coord_z = 2;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[1] .mask = 16'hB8F0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[1] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[1] .FeedbackMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[1] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[1] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[1] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[2] (
	.A(\macro_inst|rx_fifo_req [0]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [1]),
	.C(vcc),
	.D(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff~q ),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [2]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X59_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X59_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[2]~2_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [2]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[2] .coord_x = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[2] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[2] .coord_z = 1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[2] .mask = 16'hD8F0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[2] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[2] .FeedbackMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[2] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[2] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[2] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[3] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [2]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff~q ),
	.C(vcc),
	.D(\macro_inst|rx_fifo_req [0]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [3]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X59_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X59_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[3]~3_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [3]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[3] .coord_x = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[3] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[3] .coord_z = 13;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[3] .mask = 16'hB8F0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[3] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[3] .FeedbackMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[3] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[3] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[3] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[4] (
	.A(\macro_inst|rx_fifo_req [0]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff~q ),
	.C(vcc),
	.D(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [3]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [4]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X59_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X59_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[4]~4_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [4]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[4] .coord_x = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[4] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[4] .coord_z = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[4] .mask = 16'hF870;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[4] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[4] .FeedbackMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[4] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[4] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[4] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[5] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [4]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff~q ),
	.C(vcc),
	.D(\macro_inst|rx_fifo_req [0]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [5]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X59_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X59_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[5]~5_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [5]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[5] .coord_x = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[5] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[5] .coord_z = 0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[5] .mask = 16'hB8F0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[5] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[5] .FeedbackMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[5] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[5] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[5] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[6] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff~q ),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [5]),
	.C(vcc),
	.D(\macro_inst|rx_fifo_req [0]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [6]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X58_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[6]~6_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [6]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[6] .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[6] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[6] .coord_z = 2;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[6] .mask = 16'hD8F0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[6] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[6] .FeedbackMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[6] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[6] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[6] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[7] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [6]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff~q ),
	.C(vcc),
	.D(\macro_inst|rx_fifo_req [0]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [7]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X59_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X59_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[7]~7_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [7]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[7] .coord_x = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[7] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[7] .coord_z = 14;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[7] .mask = 16'hB8F0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[7] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[7] .FeedbackMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[7] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[7] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[7] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[8] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [7]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff~q ),
	.C(vcc),
	.D(\macro_inst|rx_fifo_req [0]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [8]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X58_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[8]~8_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [8]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[8] .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[8] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[8] .coord_z = 11;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[8] .mask = 16'hB8F0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[8] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[8] .FeedbackMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[8] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[8] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[8] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[9] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [8]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff~q ),
	.C(vcc),
	.D(\macro_inst|rx_fifo_req [0]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [9]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X59_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X59_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|ram_read_address[9]~9_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa [9]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[9] .coord_x = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[9] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[9] .coord_z = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[9] .mask = 16'hB8F0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[9] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[9] .FeedbackMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[9] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[9] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|low_addressa[9] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_lsb (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_lsb~q ),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout_X58_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X58_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_lsb~0_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_lsb~q ));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_lsb .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_lsb .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_lsb .coord_z = 5;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_lsb .mask = 16'h0F0F;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_lsb .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_lsb .FeedbackMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_lsb .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_lsb .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_lsb .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[0] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~9_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita0~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita0~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [0]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[0] .coord_x = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[0] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[0] .coord_z = 4;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[0] .mask = 16'h33CC;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[0] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[0] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[0] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[0] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[0] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[1] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita0~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [1]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~9_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita1~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita1~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [1]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[1] .coord_x = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[1] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[1] .coord_z = 5;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[1] .mask = 16'h3C3F;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[1] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[1] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[1] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[1] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[1] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[2] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita1~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [2]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~9_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita2~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita2~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [2]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[2] .coord_x = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[2] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[2] .coord_z = 6;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[2] .mask = 16'hC30C;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[2] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[2] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[2] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[2] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[2] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[3] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita2~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [3]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~9_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita3~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita3~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [3]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[3] .coord_x = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[3] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[3] .coord_z = 7;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[3] .mask = 16'h3C3F;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[3] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[3] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[3] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[3] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[3] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[4] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita3~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [4]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~9_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita4~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita4~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [4]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[4] .coord_x = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[4] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[4] .coord_z = 8;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[4] .mask = 16'hC30C;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[4] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[4] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[4] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[4] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[4] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[5] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita4~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [5]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~9_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita5~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita5~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [5]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[5] .coord_x = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[5] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[5] .coord_z = 9;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[5] .mask = 16'h3C3F;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[5] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[5] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[5] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[5] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[5] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[6] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita5~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [6]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~9_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita6~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita6~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [6]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[6] .coord_x = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[6] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[6] .coord_z = 10;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[6] .mask = 16'hC30C;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[6] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[6] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[6] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[6] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[6] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[7] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita6~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [7]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~9_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita7~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita7~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [7]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[7] .coord_x = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[7] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[7] .coord_z = 11;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[7] .mask = 16'h3C3F;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[7] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[7] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[7] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[7] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[7] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[8] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [8]),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita7~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [8]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~9_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_comb_bita8~combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit [8]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[8] .coord_x = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[8] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[8] .coord_z = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[8] .mask = 16'hF00F;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[8] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[8] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[8] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[8] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_msb|counter_reg_bit[8] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[0] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [0]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2_combout_X57_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita0~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita0~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [0]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[0] .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[0] .coord_y = 6;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[0] .coord_z = 5;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[0] .mask = 16'h5599;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[0] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[0] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[0] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[0] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[0] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[1] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [1]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita0~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [1]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2_combout_X57_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita1~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita1~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [1]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[1] .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[1] .coord_y = 6;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[1] .coord_z = 6;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[1] .mask = 16'h5A6F;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[1] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[1] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[1] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[1] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[1] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[2] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [2]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita1~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [2]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2_combout_X57_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita2~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita2~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [2]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[2] .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[2] .coord_y = 6;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[2] .coord_z = 7;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[2] .mask = 16'hA509;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[2] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[2] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[2] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[2] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[2] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[3] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [3]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita2~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [3]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2_combout_X57_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita3~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita3~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [3]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[3] .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[3] .coord_y = 6;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[3] .coord_z = 8;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[3] .mask = 16'h5A6F;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[3] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[3] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[3] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[3] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[3] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[4] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [4]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita3~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [4]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2_combout_X57_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita4~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita4~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [4]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[4] .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[4] .coord_y = 6;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[4] .coord_z = 9;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[4] .mask = 16'hA509;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[4] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[4] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[4] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[4] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[4] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[5] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [5]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita4~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [5]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2_combout_X57_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita5~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita5~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [5]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[5] .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[5] .coord_y = 6;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[5] .coord_z = 10;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[5] .mask = 16'h5A6F;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[5] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[5] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[5] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[5] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[5] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[6] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [6]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita5~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [6]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2_combout_X57_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita6~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita6~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [6]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[6] .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[6] .coord_y = 6;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[6] .coord_z = 11;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[6] .mask = 16'hA509;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[6] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[6] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[6] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[6] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[6] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[7] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [7]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita6~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [7]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2_combout_X57_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita7~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita7~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [7]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[7] .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[7] .coord_y = 6;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[7] .coord_z = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[7] .mask = 16'h5A6F;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[7] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[7] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[7] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[7] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[7] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[8] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [8]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita7~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [8]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2_combout_X57_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita8~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita8~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [8]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[8] .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[8] .coord_y = 6;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[8] .coord_z = 13;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[8] .mask = 16'hA509;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[8] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[8] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[8] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[8] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[8] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[9] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [9]),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita8~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [9]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~2_combout_X57_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_comb_bita9~combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [9]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[9] .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[9] .coord_y = 6;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[9] .coord_z = 14;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[9] .mask = 16'h0FF0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[9] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[9] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[9] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[9] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit[9] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_0_dff (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_1_dff~q ),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ),
	.C(vcc),
	.D(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_0_dff~q ),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X58_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~8_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_0_dff~q ));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_0_dff .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_0_dff .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_0_dff .coord_z = 1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_0_dff .mask = 16'hF374;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_0_dff .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_0_dff .FeedbackMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_0_dff .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_0_dff .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_0_dff .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_1_dff (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_1~0_combout ),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_2_dff~q ),
	.D(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_1_dff~q ),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X58_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_1~1_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_1_dff~q ));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_1_dff .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_1_dff .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_1_dff .coord_z = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_1_dff .mask = 16'hCCEC;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_1_dff .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_1_dff .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_1_dff .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_1_dff .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_1_dff .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_2_dff (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~10_combout ),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~13_combout ),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~11_combout ),
	.D(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_2~0_combout ),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_2_dff~q ),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X57_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_2~1_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_2_dff~q ));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_2_dff .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_2_dff .coord_y = 6;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_2_dff .coord_z = 2;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_2_dff .mask = 16'hFF80;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_2_dff .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_2_dff .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_2_dff .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_2_dff .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_2_dff .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_1~0 (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_1_dff~q ),
	.D(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_0_dff~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_1~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_1~0 .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_1~0 .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_1~0 .coord_z = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_1~0 .mask = 16'h90D4;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_1~0 .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_1~0 .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_1~0 .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_1~0 .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_1~0 .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_2~0 (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_2_dff~q ),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ),
	.C(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_is_1_dff~q ),
	.D(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_2~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_2~0 .coord_x = 15;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_2~0 .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_2~0 .coord_z = 0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_2~0 .mask = 16'hB822;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_2~0 .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_2~0 .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_2~0 .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_2~0 .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_will_be_2~0 .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .coord_x = 14;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .coord_z = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .mask = 16'h33CC;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .coord_x = 14;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .coord_z = 4;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .mask = 16'h3C3F;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .coord_x = 14;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .coord_z = 5;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .mask = 16'hC30C;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .coord_x = 14;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .coord_z = 6;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .mask = 16'h3C3F;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .coord_x = 14;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .coord_z = 7;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .mask = 16'hC30C;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .coord_x = 14;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .coord_z = 8;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .mask = 16'h3C3F;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .coord_x = 14;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .coord_z = 9;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .mask = 16'hC30C;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .coord_x = 14;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .coord_z = 10;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .mask = 16'h3C3F;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout ),
	.Cout(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT ),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .coord_x = 14;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .coord_z = 11;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .mask = 16'hC30C;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .CarryEnb = 1'b0;

alta_slice \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9]),
	.Cin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT ),
	.Qin(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9]));
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .coord_x = 14;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .coord_y = 3;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .coord_z = 12;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .mask = 16'h0FF0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .modeMux = 1'b1;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .BypassEn = 1'b0;
defparam \macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_req[0] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [3]),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~12_combout ),
	.C(\macro_inst|always5~0_combout ),
	.D(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|usedw_counter|counter_reg_bit [2]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_req [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X57_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y2_GND),
	.SyncReset(SyncReset_X57_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y2_VCC),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~13_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_req [0]));
defparam \macro_inst|rx_fifo_req[0] .coord_x = 15;
defparam \macro_inst|rx_fifo_req[0] .coord_y = 6;
defparam \macro_inst|rx_fifo_req[0] .coord_z = 3;
defparam \macro_inst|rx_fifo_req[0] .mask = 16'h0044;
defparam \macro_inst|rx_fifo_req[0] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_req[0] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_req[0] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_req[0] .BypassEn = 1'b1;
defparam \macro_inst|rx_fifo_req[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_wen[0] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff~q ),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|full_dff~q ),
	.C(\macro_inst|spi_inst|rx_en~q ),
	.D(\macro_inst|rx_fifo_req [0]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_wen [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X57_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y2_GND),
	.SyncReset(SyncReset_X57_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y2_VCC),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~3_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_wen [0]));
defparam \macro_inst|rx_fifo_wen[0] .coord_x = 15;
defparam \macro_inst|rx_fifo_wen[0] .coord_y = 6;
defparam \macro_inst|rx_fifo_wen[0] .coord_z = 4;
defparam \macro_inst|rx_fifo_wen[0] .mask = 16'h44CC;
defparam \macro_inst|rx_fifo_wen[0] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_wen[0] .FeedbackMux = 1'b0;
defparam \macro_inst|rx_fifo_wen[0] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_wen[0] .BypassEn = 1'b1;
defparam \macro_inst|rx_fifo_wen[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|rx_fifo_wen_r[0] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff~q ),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|full_dff~q ),
	.C(\macro_inst|rx_fifo_wen [0]),
	.D(\macro_inst|rx_fifo_req [0]),
	.Cin(),
	.Qin(\macro_inst|rx_fifo_wen_r [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X57_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y2_GND),
	.SyncReset(SyncReset_X57_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y2_VCC),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~10_combout ),
	.Cout(),
	.Q(\macro_inst|rx_fifo_wen_r [0]));
defparam \macro_inst|rx_fifo_wen_r[0] .coord_x = 15;
defparam \macro_inst|rx_fifo_wen_r[0] .coord_y = 6;
defparam \macro_inst|rx_fifo_wen_r[0] .coord_z = 0;
defparam \macro_inst|rx_fifo_wen_r[0] .mask = 16'h8A00;
defparam \macro_inst|rx_fifo_wen_r[0] .modeMux = 1'b0;
defparam \macro_inst|rx_fifo_wen_r[0] .FeedbackMux = 1'b1;
defparam \macro_inst|rx_fifo_wen_r[0] .ShiftMux = 1'b0;
defparam \macro_inst|rx_fifo_wen_r[0] .BypassEn = 1'b1;
defparam \macro_inst|rx_fifo_wen_r[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|Add0~0 (
	.A(vcc),
	.B(\macro_inst|spi_inst|sck_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|Add0~0_combout ),
	.Cout(\macro_inst|spi_inst|Add0~1 ),
	.Q());
defparam \macro_inst|spi_inst|Add0~0 .coord_x = 14;
defparam \macro_inst|spi_inst|Add0~0 .coord_y = 2;
defparam \macro_inst|spi_inst|Add0~0 .coord_z = 6;
defparam \macro_inst|spi_inst|Add0~0 .mask = 16'hCC33;
defparam \macro_inst|spi_inst|Add0~0 .modeMux = 1'b0;
defparam \macro_inst|spi_inst|Add0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|Add0~0 .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|Add0~0 .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|Add0~0 .CarryEnb = 1'b0;

alta_slice \macro_inst|spi_inst|Add0~3 (
	.A(vcc),
	.B(\macro_inst|spi_inst|sck_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|spi_inst|Add0~1 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|Add0~3_combout ),
	.Cout(\macro_inst|spi_inst|Add0~4 ),
	.Q());
defparam \macro_inst|spi_inst|Add0~3 .coord_x = 14;
defparam \macro_inst|spi_inst|Add0~3 .coord_y = 2;
defparam \macro_inst|spi_inst|Add0~3 .coord_z = 7;
defparam \macro_inst|spi_inst|Add0~3 .mask = 16'hC3CF;
defparam \macro_inst|spi_inst|Add0~3 .modeMux = 1'b1;
defparam \macro_inst|spi_inst|Add0~3 .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|Add0~3 .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|Add0~3 .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|Add0~3 .CarryEnb = 1'b0;

alta_slice \macro_inst|spi_inst|Add0~6 (
	.A(\macro_inst|spi_inst|sck_cnt [2]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|spi_inst|Add0~4 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|Add0~6_combout ),
	.Cout(\macro_inst|spi_inst|Add0~7 ),
	.Q());
defparam \macro_inst|spi_inst|Add0~6 .coord_x = 14;
defparam \macro_inst|spi_inst|Add0~6 .coord_y = 2;
defparam \macro_inst|spi_inst|Add0~6 .coord_z = 8;
defparam \macro_inst|spi_inst|Add0~6 .mask = 16'h5A05;
defparam \macro_inst|spi_inst|Add0~6 .modeMux = 1'b1;
defparam \macro_inst|spi_inst|Add0~6 .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|Add0~6 .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|Add0~6 .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|Add0~6 .CarryEnb = 1'b0;

alta_slice \macro_inst|spi_inst|Equal0~0 (
	.A(\macro_inst|spi_inst|sck_cnt [1]),
	.B(\macro_inst|spi_inst|sck_cnt [4]),
	.C(\macro_inst|spi_inst|sck_cnt [3]),
	.D(\macro_inst|spi_inst|sck_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|Equal0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|spi_inst|Equal0~0 .coord_x = 14;
defparam \macro_inst|spi_inst|Equal0~0 .coord_y = 5;
defparam \macro_inst|spi_inst|Equal0~0 .coord_z = 15;
defparam \macro_inst|spi_inst|Equal0~0 .mask = 16'h1000;
defparam \macro_inst|spi_inst|Equal0~0 .modeMux = 1'b0;
defparam \macro_inst|spi_inst|Equal0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|Equal0~0 .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|Equal0~0 .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|Equal0~0 .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|csen_r[0] (
	.A(\macro_inst|spi_inst|sck_cnt [2]),
	.B(\macro_inst|spi_inst|sck_cnt [1]),
	.C(\macro_inst|csen [0]),
	.D(\macro_inst|spi_inst|sck_cnt [0]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|csen_r [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X50_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X50_Y2_GND),
	.SyncReset(SyncReset_X50_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X50_Y2_VCC),
	.LutOut(\macro_inst|spi_inst|scs~0_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|csen_r [0]));
defparam \macro_inst|spi_inst|csen_r[0] .coord_x = 14;
defparam \macro_inst|spi_inst|csen_r[0] .coord_y = 2;
defparam \macro_inst|spi_inst|csen_r[0] .coord_z = 15;
defparam \macro_inst|spi_inst|csen_r[0] .mask = 16'h0011;
defparam \macro_inst|spi_inst|csen_r[0] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|csen_r[0] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|csen_r[0] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|csen_r[0] .BypassEn = 1'b1;
defparam \macro_inst|spi_inst|csen_r[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|rx_data[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|spi_inst|rx_data_r [0]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|rx_data [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always9~0_combout_X51_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|rx_data[0]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|rx_data [0]));
defparam \macro_inst|spi_inst|rx_data[0] .coord_x = 17;
defparam \macro_inst|spi_inst|rx_data[0] .coord_y = 3;
defparam \macro_inst|spi_inst|rx_data[0] .coord_z = 10;
defparam \macro_inst|spi_inst|rx_data[0] .mask = 16'hFF00;
defparam \macro_inst|spi_inst|rx_data[0] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[0] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[0] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[0] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|rx_data[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|rx_data[1] (
	.A(),
	.B(),
	.C(\macro_inst|spi_inst|rx_data_r [1]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|spi_inst|rx_data [1]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always9~0_combout_X51_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(SyncReset_X51_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X51_Y1_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|spi_inst|rx_data [1]));
defparam \macro_inst|spi_inst|rx_data[1] .coord_x = 17;
defparam \macro_inst|spi_inst|rx_data[1] .coord_y = 3;
defparam \macro_inst|spi_inst|rx_data[1] .coord_z = 7;
defparam \macro_inst|spi_inst|rx_data[1] .mask = 16'hFFFF;
defparam \macro_inst|spi_inst|rx_data[1] .modeMux = 1'b1;
defparam \macro_inst|spi_inst|rx_data[1] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[1] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[1] .BypassEn = 1'b1;
defparam \macro_inst|spi_inst|rx_data[1] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|rx_data[2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|spi_inst|rx_data_r [2]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|rx_data [2]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always9~0_combout_X51_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|rx_data[2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|rx_data [2]));
defparam \macro_inst|spi_inst|rx_data[2] .coord_x = 17;
defparam \macro_inst|spi_inst|rx_data[2] .coord_y = 3;
defparam \macro_inst|spi_inst|rx_data[2] .coord_z = 8;
defparam \macro_inst|spi_inst|rx_data[2] .mask = 16'hFF00;
defparam \macro_inst|spi_inst|rx_data[2] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[2] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[2] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[2] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|rx_data[2] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|rx_data[3] (
	.A(),
	.B(),
	.C(\macro_inst|spi_inst|rx_data_r [3]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|spi_inst|rx_data [3]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always9~0_combout_X51_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(SyncReset_X51_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X51_Y1_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|spi_inst|rx_data [3]));
defparam \macro_inst|spi_inst|rx_data[3] .coord_x = 17;
defparam \macro_inst|spi_inst|rx_data[3] .coord_y = 3;
defparam \macro_inst|spi_inst|rx_data[3] .coord_z = 2;
defparam \macro_inst|spi_inst|rx_data[3] .mask = 16'hFFFF;
defparam \macro_inst|spi_inst|rx_data[3] .modeMux = 1'b1;
defparam \macro_inst|spi_inst|rx_data[3] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[3] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[3] .BypassEn = 1'b1;
defparam \macro_inst|spi_inst|rx_data[3] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|rx_data[4] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|spi_inst|rx_data_r [4]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|spi_inst|rx_data [4]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always9~0_combout_X51_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(SyncReset_X51_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X51_Y1_VCC),
	.LutOut(slave_ahb_haddr[24]),
	.Cout(),
	.Q(\macro_inst|spi_inst|rx_data [4]));
defparam \macro_inst|spi_inst|rx_data[4] .coord_x = 17;
defparam \macro_inst|spi_inst|rx_data[4] .coord_y = 3;
defparam \macro_inst|spi_inst|rx_data[4] .coord_z = 0;
defparam \macro_inst|spi_inst|rx_data[4] .mask = 16'h0000;
defparam \macro_inst|spi_inst|rx_data[4] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[4] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[4] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[4] .BypassEn = 1'b1;
defparam \macro_inst|spi_inst|rx_data[4] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|rx_data[5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|spi_inst|rx_data_r [5]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|rx_data [5]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always9~0_combout_X51_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|rx_data[5]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|rx_data [5]));
defparam \macro_inst|spi_inst|rx_data[5] .coord_x = 17;
defparam \macro_inst|spi_inst|rx_data[5] .coord_y = 3;
defparam \macro_inst|spi_inst|rx_data[5] .coord_z = 6;
defparam \macro_inst|spi_inst|rx_data[5] .mask = 16'hFF00;
defparam \macro_inst|spi_inst|rx_data[5] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[5] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[5] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[5] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|rx_data[5] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|rx_data[6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|spi_inst|rx_data_r [6]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|rx_data [6]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always9~0_combout_X51_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|rx_data[6]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|rx_data [6]));
defparam \macro_inst|spi_inst|rx_data[6] .coord_x = 17;
defparam \macro_inst|spi_inst|rx_data[6] .coord_y = 3;
defparam \macro_inst|spi_inst|rx_data[6] .coord_z = 15;
defparam \macro_inst|spi_inst|rx_data[6] .mask = 16'hFF00;
defparam \macro_inst|spi_inst|rx_data[6] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[6] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[6] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[6] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|rx_data[6] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|rx_data[7] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|spi_inst|rx_data_r [7]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|rx_data [7]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always9~0_combout_X51_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|rx_data[7]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|rx_data [7]));
defparam \macro_inst|spi_inst|rx_data[7] .coord_x = 17;
defparam \macro_inst|spi_inst|rx_data[7] .coord_y = 3;
defparam \macro_inst|spi_inst|rx_data[7] .coord_z = 1;
defparam \macro_inst|spi_inst|rx_data[7] .mask = 16'hFF00;
defparam \macro_inst|spi_inst|rx_data[7] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[7] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[7] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data[7] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|rx_data[7] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|rx_data_r[0] (
	.A(),
	.B(),
	.C(\PIN_58~input_o ),
	.D(),
	.Cin(),
	.Qin(\macro_inst|spi_inst|rx_data_r [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always7~0_combout_X51_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(SyncReset_X51_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X51_Y1_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|spi_inst|rx_data_r [0]));
defparam \macro_inst|spi_inst|rx_data_r[0] .coord_x = 17;
defparam \macro_inst|spi_inst|rx_data_r[0] .coord_y = 3;
defparam \macro_inst|spi_inst|rx_data_r[0] .coord_z = 11;
defparam \macro_inst|spi_inst|rx_data_r[0] .mask = 16'hFFFF;
defparam \macro_inst|spi_inst|rx_data_r[0] .modeMux = 1'b1;
defparam \macro_inst|spi_inst|rx_data_r[0] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[0] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[0] .BypassEn = 1'b1;
defparam \macro_inst|spi_inst|rx_data_r[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|rx_data_r[1] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|spi_inst|rx_data_r [0]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|rx_data_r [1]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always7~0_combout_X51_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|rx_data_r[1]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|rx_data_r [1]));
defparam \macro_inst|spi_inst|rx_data_r[1] .coord_x = 17;
defparam \macro_inst|spi_inst|rx_data_r[1] .coord_y = 3;
defparam \macro_inst|spi_inst|rx_data_r[1] .coord_z = 4;
defparam \macro_inst|spi_inst|rx_data_r[1] .mask = 16'hFF00;
defparam \macro_inst|spi_inst|rx_data_r[1] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[1] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[1] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[1] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[1] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|rx_data_r[2] (
	.A(),
	.B(),
	.C(\macro_inst|spi_inst|rx_data_r [1]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|spi_inst|rx_data_r [2]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always7~0_combout_X51_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(SyncReset_X51_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X51_Y1_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|spi_inst|rx_data_r [2]));
defparam \macro_inst|spi_inst|rx_data_r[2] .coord_x = 17;
defparam \macro_inst|spi_inst|rx_data_r[2] .coord_y = 3;
defparam \macro_inst|spi_inst|rx_data_r[2] .coord_z = 5;
defparam \macro_inst|spi_inst|rx_data_r[2] .mask = 16'hFFFF;
defparam \macro_inst|spi_inst|rx_data_r[2] .modeMux = 1'b1;
defparam \macro_inst|spi_inst|rx_data_r[2] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[2] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[2] .BypassEn = 1'b1;
defparam \macro_inst|spi_inst|rx_data_r[2] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|rx_data_r[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|spi_inst|rx_data_r [2]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|rx_data_r [3]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always7~0_combout_X51_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|rx_data_r[3]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|rx_data_r [3]));
defparam \macro_inst|spi_inst|rx_data_r[3] .coord_x = 17;
defparam \macro_inst|spi_inst|rx_data_r[3] .coord_y = 3;
defparam \macro_inst|spi_inst|rx_data_r[3] .coord_z = 14;
defparam \macro_inst|spi_inst|rx_data_r[3] .mask = 16'hFF00;
defparam \macro_inst|spi_inst|rx_data_r[3] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[3] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[3] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[3] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[3] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|rx_data_r[4] (
	.A(),
	.B(),
	.C(\macro_inst|spi_inst|rx_data_r [3]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|spi_inst|rx_data_r [4]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always7~0_combout_X51_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(SyncReset_X51_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X51_Y1_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|spi_inst|rx_data_r [4]));
defparam \macro_inst|spi_inst|rx_data_r[4] .coord_x = 17;
defparam \macro_inst|spi_inst|rx_data_r[4] .coord_y = 3;
defparam \macro_inst|spi_inst|rx_data_r[4] .coord_z = 12;
defparam \macro_inst|spi_inst|rx_data_r[4] .mask = 16'hFFFF;
defparam \macro_inst|spi_inst|rx_data_r[4] .modeMux = 1'b1;
defparam \macro_inst|spi_inst|rx_data_r[4] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[4] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[4] .BypassEn = 1'b1;
defparam \macro_inst|spi_inst|rx_data_r[4] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|rx_data_r[5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|spi_inst|rx_data_r [4]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|rx_data_r [5]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always7~0_combout_X51_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|rx_data_r[5]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|rx_data_r [5]));
defparam \macro_inst|spi_inst|rx_data_r[5] .coord_x = 17;
defparam \macro_inst|spi_inst|rx_data_r[5] .coord_y = 3;
defparam \macro_inst|spi_inst|rx_data_r[5] .coord_z = 13;
defparam \macro_inst|spi_inst|rx_data_r[5] .mask = 16'hFF00;
defparam \macro_inst|spi_inst|rx_data_r[5] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[5] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[5] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[5] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[5] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|rx_data_r[6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|spi_inst|rx_data_r [5]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|rx_data_r [6]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always7~0_combout_X51_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|rx_data_r[6]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|rx_data_r [6]));
defparam \macro_inst|spi_inst|rx_data_r[6] .coord_x = 17;
defparam \macro_inst|spi_inst|rx_data_r[6] .coord_y = 3;
defparam \macro_inst|spi_inst|rx_data_r[6] .coord_z = 9;
defparam \macro_inst|spi_inst|rx_data_r[6] .mask = 16'hFF00;
defparam \macro_inst|spi_inst|rx_data_r[6] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[6] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[6] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[6] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[6] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|rx_data_r[7] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|spi_inst|rx_data_r [6]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|rx_data_r [7]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|always7~0_combout_X51_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|rx_data_r[7]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|rx_data_r [7]));
defparam \macro_inst|spi_inst|rx_data_r[7] .coord_x = 17;
defparam \macro_inst|spi_inst|rx_data_r[7] .coord_y = 3;
defparam \macro_inst|spi_inst|rx_data_r[7] .coord_z = 3;
defparam \macro_inst|spi_inst|rx_data_r[7] .mask = 16'hFF00;
defparam \macro_inst|spi_inst|rx_data_r[7] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[7] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[7] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[7] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|rx_data_r[7] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|rx_en (
	.A(\macro_inst|spi_inst|csen_r [0]),
	.B(\macro_inst|spi_inst|sck_r [0]),
	.C(\macro_inst|spi_inst|sck_cnt_bit0 [0]),
	.D(\macro_inst|spi_inst|sck~q ),
	.Cin(),
	.Qin(\macro_inst|spi_inst|rx_en~q ),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X53_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X53_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|always9~0_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|rx_en~q ));
defparam \macro_inst|spi_inst|rx_en .coord_x = 15;
defparam \macro_inst|spi_inst|rx_en .coord_y = 4;
defparam \macro_inst|spi_inst|rx_en .coord_z = 5;
defparam \macro_inst|spi_inst|rx_en .mask = 16'h3004;
defparam \macro_inst|spi_inst|rx_en .modeMux = 1'b0;
defparam \macro_inst|spi_inst|rx_en .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|rx_en .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|rx_en .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|rx_en .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|sck (
	.A(),
	.B(),
	.C(\macro_inst|spi_inst|sck_cnt_bit0 [0]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|spi_inst|sck~q ),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(SyncReset_X52_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X52_Y1_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|spi_inst|sck~q ));
defparam \macro_inst|spi_inst|sck .coord_x = 16;
defparam \macro_inst|spi_inst|sck .coord_y = 3;
defparam \macro_inst|spi_inst|sck .coord_z = 4;
defparam \macro_inst|spi_inst|sck .mask = 16'hFFFF;
defparam \macro_inst|spi_inst|sck .modeMux = 1'b1;
defparam \macro_inst|spi_inst|sck .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|sck .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|sck .BypassEn = 1'b1;
defparam \macro_inst|spi_inst|sck .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|sck_cnt[0] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|spi_inst|Add0~0_combout ),
	.D(\macro_inst|spi_inst|tx_en_r [7]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|sck_cnt [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|sck_cnt[0]~0_combout_X50_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X50_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|Add0~2_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|sck_cnt [0]));
defparam \macro_inst|spi_inst|sck_cnt[0] .coord_x = 14;
defparam \macro_inst|spi_inst|sck_cnt[0] .coord_y = 2;
defparam \macro_inst|spi_inst|sck_cnt[0] .coord_z = 11;
defparam \macro_inst|spi_inst|sck_cnt[0] .mask = 16'hFF0F;
defparam \macro_inst|spi_inst|sck_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|sck_cnt[0]~0 (
	.A(\macro_inst|spi_inst|sck_cnt [4]),
	.B(\macro_inst|spi_inst|scs~0_combout ),
	.C(\macro_inst|spi_inst|sck_cnt [3]),
	.D(\macro_inst|spi_inst|tx_en_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|sck_cnt[0]~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|spi_inst|sck_cnt[0]~0 .coord_x = 14;
defparam \macro_inst|spi_inst|sck_cnt[0]~0 .coord_y = 2;
defparam \macro_inst|spi_inst|sck_cnt[0]~0 .coord_z = 2;
defparam \macro_inst|spi_inst|sck_cnt[0]~0 .mask = 16'hFFFB;
defparam \macro_inst|spi_inst|sck_cnt[0]~0 .modeMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[0]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[0]~0 .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[0]~0 .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[0]~0 .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|sck_cnt[1] (
	.A(vcc),
	.B(\macro_inst|spi_inst|Add0~3_combout ),
	.C(vcc),
	.D(\macro_inst|spi_inst|tx_en_r [7]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|sck_cnt [1]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|sck_cnt[0]~0_combout_X50_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X50_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|Add0~5_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|sck_cnt [1]));
defparam \macro_inst|spi_inst|sck_cnt[1] .coord_x = 14;
defparam \macro_inst|spi_inst|sck_cnt[1] .coord_y = 2;
defparam \macro_inst|spi_inst|sck_cnt[1] .coord_z = 5;
defparam \macro_inst|spi_inst|sck_cnt[1] .mask = 16'hFF33;
defparam \macro_inst|spi_inst|sck_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[1] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|sck_cnt[2] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|spi_inst|Add0~6_combout ),
	.D(\macro_inst|spi_inst|tx_en_r [7]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|sck_cnt [2]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|sck_cnt[0]~0_combout_X50_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X50_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|Add0~8_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|sck_cnt [2]));
defparam \macro_inst|spi_inst|sck_cnt[2] .coord_x = 14;
defparam \macro_inst|spi_inst|sck_cnt[2] .coord_y = 2;
defparam \macro_inst|spi_inst|sck_cnt[2] .coord_z = 14;
defparam \macro_inst|spi_inst|sck_cnt[2] .mask = 16'hFF0F;
defparam \macro_inst|spi_inst|sck_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[2] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|sck_cnt[3] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|spi_inst|Add0~9_combout ),
	.D(\macro_inst|spi_inst|tx_en_r [7]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|sck_cnt [3]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|sck_cnt[0]~0_combout_X50_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X50_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|Add0~14_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|sck_cnt [3]));
defparam \macro_inst|spi_inst|sck_cnt[3] .coord_x = 14;
defparam \macro_inst|spi_inst|sck_cnt[3] .coord_y = 2;
defparam \macro_inst|spi_inst|sck_cnt[3] .coord_z = 4;
defparam \macro_inst|spi_inst|sck_cnt[3] .mask = 16'hFF0F;
defparam \macro_inst|spi_inst|sck_cnt[3] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[3] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[3] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|sck_cnt[4] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|spi_inst|Add0~11_combout ),
	.D(\macro_inst|spi_inst|tx_en_r [7]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|sck_cnt [4]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|sck_cnt[0]~0_combout_X50_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X50_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|Add0~13_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|sck_cnt [4]));
defparam \macro_inst|spi_inst|sck_cnt[4] .coord_x = 14;
defparam \macro_inst|spi_inst|sck_cnt[4] .coord_y = 2;
defparam \macro_inst|spi_inst|sck_cnt[4] .coord_z = 0;
defparam \macro_inst|spi_inst|sck_cnt[4] .mask = 16'hFF0F;
defparam \macro_inst|spi_inst|sck_cnt[4] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[4] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[4] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[4] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt[4] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|sck_cnt_bit0[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|spi_inst|sck_cnt_bit0~1_combout ),
	.Cin(),
	.Qin(\macro_inst|spi_inst|sck_cnt_bit0 [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|sck_cnt_bit0[0]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|sck_cnt_bit0 [0]));
defparam \macro_inst|spi_inst|sck_cnt_bit0[0] .coord_x = 16;
defparam \macro_inst|spi_inst|sck_cnt_bit0[0] .coord_y = 3;
defparam \macro_inst|spi_inst|sck_cnt_bit0[0] .coord_z = 14;
defparam \macro_inst|spi_inst|sck_cnt_bit0[0] .mask = 16'hFF00;
defparam \macro_inst|spi_inst|sck_cnt_bit0[0] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt_bit0[0] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt_bit0[0] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt_bit0[0] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt_bit0[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|sck_cnt_bit0~0 (
	.A(\macro_inst|spi_inst|csen_r [0]),
	.B(\macro_inst|spi_inst|sck_cnt [1]),
	.C(\macro_inst|spi_inst|sck_cnt [2]),
	.D(\macro_inst|spi_inst|sck_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|sck_cnt_bit0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|spi_inst|sck_cnt_bit0~0 .coord_x = 14;
defparam \macro_inst|spi_inst|sck_cnt_bit0~0 .coord_y = 2;
defparam \macro_inst|spi_inst|sck_cnt_bit0~0 .coord_z = 1;
defparam \macro_inst|spi_inst|sck_cnt_bit0~0 .mask = 16'hAAA8;
defparam \macro_inst|spi_inst|sck_cnt_bit0~0 .modeMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt_bit0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt_bit0~0 .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt_bit0~0 .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt_bit0~0 .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|sck_cnt_bit0~1 (
	.A(\macro_inst|spi_inst|sck_cnt_bit0~0_combout ),
	.B(\macro_inst|spi_inst|sck_cnt [4]),
	.C(\macro_inst|spi_inst|sck_cnt [3]),
	.D(\macro_inst|spi_inst|sck_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|sck_cnt_bit0~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|spi_inst|sck_cnt_bit0~1 .coord_x = 14;
defparam \macro_inst|spi_inst|sck_cnt_bit0~1 .coord_y = 5;
defparam \macro_inst|spi_inst|sck_cnt_bit0~1 .coord_z = 4;
defparam \macro_inst|spi_inst|sck_cnt_bit0~1 .mask = 16'h20EC;
defparam \macro_inst|spi_inst|sck_cnt_bit0~1 .modeMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt_bit0~1 .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt_bit0~1 .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt_bit0~1 .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|sck_cnt_bit0~1 .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|sck_r[0] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|spi_inst|sck~q ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|spi_inst|sck_r [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X53_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X53_Y1_GND),
	.SyncReset(SyncReset_X53_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y1_VCC),
	.LutOut(gpio8_io_in[4]),
	.Cout(),
	.Q(\macro_inst|spi_inst|sck_r [0]));
defparam \macro_inst|spi_inst|sck_r[0] .coord_x = 15;
defparam \macro_inst|spi_inst|sck_r[0] .coord_y = 4;
defparam \macro_inst|spi_inst|sck_r[0] .coord_z = 11;
defparam \macro_inst|spi_inst|sck_r[0] .mask = 16'h0000;
defparam \macro_inst|spi_inst|sck_r[0] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|sck_r[0] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|sck_r[0] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|sck_r[0] .BypassEn = 1'b1;
defparam \macro_inst|spi_inst|sck_r[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|scs (
	.A(\macro_inst|spi_inst|sck_cnt [3]),
	.B(\macro_inst|spi_inst|sck_cnt [4]),
	.C(\macro_inst|spi_inst|csen_r [0]),
	.D(\macro_inst|spi_inst|scs~0_combout ),
	.Cin(),
	.Qin(\macro_inst|spi_inst|scs~q ),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X50_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X50_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|scs~1_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|scs~q ));
defparam \macro_inst|spi_inst|scs .coord_x = 14;
defparam \macro_inst|spi_inst|scs .coord_y = 2;
defparam \macro_inst|spi_inst|scs .coord_z = 12;
defparam \macro_inst|spi_inst|scs .mask = 16'h0100;
defparam \macro_inst|spi_inst|scs .modeMux = 1'b0;
defparam \macro_inst|spi_inst|scs .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|scs .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|scs .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|scs .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_data_r[0] (
	.A(\macro_inst|tx_en [0]),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [9]),
	.C(vcc),
	.D(\macro_inst|spi_inst|tx_data_r~8_combout ),
	.Cin(),
	.Qin(\macro_inst|spi_inst|tx_data_r [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X54_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X54_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|tx_data_r~9_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|tx_data_r [0]));
defparam \macro_inst|spi_inst|tx_data_r[0] .coord_x = 14;
defparam \macro_inst|spi_inst|tx_data_r[0] .coord_y = 4;
defparam \macro_inst|spi_inst|tx_data_r[0] .coord_z = 13;
defparam \macro_inst|spi_inst|tx_data_r[0] .mask = 16'h0072;
defparam \macro_inst|spi_inst|tx_data_r[0] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[0] .FeedbackMux = 1'b1;
defparam \macro_inst|spi_inst|tx_data_r[0] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[0] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_data_r[1] (
	.A(),
	.B(),
	.C(\macro_inst|spi_inst|tx_data_r~7_combout ),
	.D(),
	.Cin(),
	.Qin(\macro_inst|spi_inst|tx_data_r [1]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|tx_data_r[7]~1_combout_X53_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X53_Y1_GND),
	.SyncReset(SyncReset_X53_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y1_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|spi_inst|tx_data_r [1]));
defparam \macro_inst|spi_inst|tx_data_r[1] .coord_x = 15;
defparam \macro_inst|spi_inst|tx_data_r[1] .coord_y = 4;
defparam \macro_inst|spi_inst|tx_data_r[1] .coord_z = 9;
defparam \macro_inst|spi_inst|tx_data_r[1] .mask = 16'hFFFF;
defparam \macro_inst|spi_inst|tx_data_r[1] .modeMux = 1'b1;
defparam \macro_inst|spi_inst|tx_data_r[1] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[1] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[1] .BypassEn = 1'b1;
defparam \macro_inst|spi_inst|tx_data_r[1] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_data_r[2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|spi_inst|tx_data_r~6_combout ),
	.Cin(),
	.Qin(\macro_inst|spi_inst|tx_data_r [2]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|tx_data_r[7]~1_combout_X53_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X53_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|tx_data_r[2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|tx_data_r [2]));
defparam \macro_inst|spi_inst|tx_data_r[2] .coord_x = 15;
defparam \macro_inst|spi_inst|tx_data_r[2] .coord_y = 4;
defparam \macro_inst|spi_inst|tx_data_r[2] .coord_z = 12;
defparam \macro_inst|spi_inst|tx_data_r[2] .mask = 16'hFF00;
defparam \macro_inst|spi_inst|tx_data_r[2] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[2] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[2] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[2] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[2] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_data_r[3] (
	.A(\macro_inst|spi_inst|tx_data_r [2]),
	.B(vcc),
	.C(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [12]),
	.D(\macro_inst|tx_en [0]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|tx_data_r [3]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|tx_data_r[7]~1_combout_X53_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X53_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|tx_data_r~5_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|tx_data_r [3]));
defparam \macro_inst|spi_inst|tx_data_r[3] .coord_x = 15;
defparam \macro_inst|spi_inst|tx_data_r[3] .coord_y = 4;
defparam \macro_inst|spi_inst|tx_data_r[3] .coord_z = 2;
defparam \macro_inst|spi_inst|tx_data_r[3] .mask = 16'h0FAA;
defparam \macro_inst|spi_inst|tx_data_r[3] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[3] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[3] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[3] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[3] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_data_r[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|spi_inst|tx_data_r~4_combout ),
	.Cin(),
	.Qin(\macro_inst|spi_inst|tx_data_r [4]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|tx_data_r[7]~1_combout_X53_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X53_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|tx_data_r[4]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|tx_data_r [4]));
defparam \macro_inst|spi_inst|tx_data_r[4] .coord_x = 15;
defparam \macro_inst|spi_inst|tx_data_r[4] .coord_y = 4;
defparam \macro_inst|spi_inst|tx_data_r[4] .coord_z = 8;
defparam \macro_inst|spi_inst|tx_data_r[4] .mask = 16'hFF00;
defparam \macro_inst|spi_inst|tx_data_r[4] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[4] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[4] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[4] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[4] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_data_r[5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|spi_inst|tx_data_r~3_combout ),
	.Cin(),
	.Qin(\macro_inst|spi_inst|tx_data_r [5]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|tx_data_r[7]~1_combout_X53_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X53_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|tx_data_r[5]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|tx_data_r [5]));
defparam \macro_inst|spi_inst|tx_data_r[5] .coord_x = 15;
defparam \macro_inst|spi_inst|tx_data_r[5] .coord_y = 4;
defparam \macro_inst|spi_inst|tx_data_r[5] .coord_z = 6;
defparam \macro_inst|spi_inst|tx_data_r[5] .mask = 16'hFF00;
defparam \macro_inst|spi_inst|tx_data_r[5] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[5] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[5] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[5] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[5] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_data_r[6] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [15]),
	.C(\macro_inst|spi_inst|tx_data_r [5]),
	.D(\macro_inst|tx_en [0]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|tx_data_r [6]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|tx_data_r[7]~1_combout_X53_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X53_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|tx_data_r~2_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|tx_data_r [6]));
defparam \macro_inst|spi_inst|tx_data_r[6] .coord_x = 15;
defparam \macro_inst|spi_inst|tx_data_r[6] .coord_y = 4;
defparam \macro_inst|spi_inst|tx_data_r[6] .coord_z = 13;
defparam \macro_inst|spi_inst|tx_data_r[6] .mask = 16'h33F0;
defparam \macro_inst|spi_inst|tx_data_r[6] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[6] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[6] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[6] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[6] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_data_r[7] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|spi_inst|tx_data_r~0_combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|spi_inst|tx_data_r [7]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|spi_inst|tx_data_r[7]~1_combout_X53_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X53_Y1_GND),
	.SyncReset(SyncReset_X53_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y1_VCC),
	.LutOut(slave_ahb_haddr[0]),
	.Cout(),
	.Q(\macro_inst|spi_inst|tx_data_r [7]));
defparam \macro_inst|spi_inst|tx_data_r[7] .coord_x = 15;
defparam \macro_inst|spi_inst|tx_data_r[7] .coord_y = 4;
defparam \macro_inst|spi_inst|tx_data_r[7] .coord_z = 4;
defparam \macro_inst|spi_inst|tx_data_r[7] .mask = 16'h0000;
defparam \macro_inst|spi_inst|tx_data_r[7] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[7] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[7] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[7] .BypassEn = 1'b1;
defparam \macro_inst|spi_inst|tx_data_r[7] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_data_r[7]~1 (
	.A(\macro_inst|spi_inst|sck~q ),
	.B(\macro_inst|spi_inst|sck_r [0]),
	.C(\macro_inst|spi_inst|sck_cnt_bit0 [0]),
	.D(\macro_inst|tx_en [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|tx_data_r[7]~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|spi_inst|tx_data_r[7]~1 .coord_x = 15;
defparam \macro_inst|spi_inst|tx_data_r[7]~1 .coord_y = 4;
defparam \macro_inst|spi_inst|tx_data_r[7]~1 .coord_z = 1;
defparam \macro_inst|spi_inst|tx_data_r[7]~1 .mask = 16'hFF02;
defparam \macro_inst|spi_inst|tx_data_r[7]~1 .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[7]~1 .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[7]~1 .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[7]~1 .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r[7]~1 .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_data_r~0 (
	.A(vcc),
	.B(\macro_inst|spi_inst|tx_data_r [6]),
	.C(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [16]),
	.D(\macro_inst|tx_en [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|tx_data_r~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|spi_inst|tx_data_r~0 .coord_x = 14;
defparam \macro_inst|spi_inst|tx_data_r~0 .coord_y = 4;
defparam \macro_inst|spi_inst|tx_data_r~0 .coord_z = 10;
defparam \macro_inst|spi_inst|tx_data_r~0 .mask = 16'h0FCC;
defparam \macro_inst|spi_inst|tx_data_r~0 .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r~0 .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r~0 .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r~0 .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r~0 .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_data_r~6 (
	.A(vcc),
	.B(\macro_inst|spi_inst|tx_data_r [1]),
	.C(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [11]),
	.D(\macro_inst|tx_en [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|tx_data_r~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|spi_inst|tx_data_r~6 .coord_x = 14;
defparam \macro_inst|spi_inst|tx_data_r~6 .coord_y = 4;
defparam \macro_inst|spi_inst|tx_data_r~6 .coord_z = 12;
defparam \macro_inst|spi_inst|tx_data_r~6 .mask = 16'h0FCC;
defparam \macro_inst|spi_inst|tx_data_r~6 .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r~6 .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r~6 .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r~6 .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r~6 .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_data_r~8 (
	.A(\macro_inst|spi_inst|sck~q ),
	.B(\macro_inst|spi_inst|sck_r [0]),
	.C(\macro_inst|spi_inst|sck_cnt_bit0 [0]),
	.D(\macro_inst|tx_en [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|tx_data_r~8_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|spi_inst|tx_data_r~8 .coord_x = 15;
defparam \macro_inst|spi_inst|tx_data_r~8 .coord_y = 4;
defparam \macro_inst|spi_inst|tx_data_r~8 .coord_z = 7;
defparam \macro_inst|spi_inst|tx_data_r~8 .mask = 16'h0002;
defparam \macro_inst|spi_inst|tx_data_r~8 .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r~8 .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r~8 .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r~8 .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|tx_data_r~8 .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_en_r[0] (
	.A(\macro_inst|spi_inst|tx_data_r [4]),
	.B(vcc),
	.C(\macro_inst|tx_en [0]),
	.D(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [14]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|tx_en_r [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X54_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X54_Y1_GND),
	.SyncReset(SyncReset_X54_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X54_Y1_VCC),
	.LutOut(\macro_inst|spi_inst|tx_data_r~3_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|tx_en_r [0]));
defparam \macro_inst|spi_inst|tx_en_r[0] .coord_x = 14;
defparam \macro_inst|spi_inst|tx_en_r[0] .coord_y = 4;
defparam \macro_inst|spi_inst|tx_en_r[0] .coord_z = 14;
defparam \macro_inst|spi_inst|tx_en_r[0] .mask = 16'h0AFA;
defparam \macro_inst|spi_inst|tx_en_r[0] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[0] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[0] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[0] .BypassEn = 1'b1;
defparam \macro_inst|spi_inst|tx_en_r[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_en_r[1] (
	.A(vcc),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|full_dff~q ),
	.C(\macro_inst|spi_inst|tx_en_r [0]),
	.D(\macro_inst|rx_fifo_wen_r [0]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|tx_en_r [1]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X58_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y2_GND),
	.SyncReset(SyncReset_X58_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y2_VCC),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|tx_en_r [1]));
defparam \macro_inst|spi_inst|tx_en_r[1] .coord_x = 15;
defparam \macro_inst|spi_inst|tx_en_r[1] .coord_y = 3;
defparam \macro_inst|spi_inst|tx_en_r[1] .coord_z = 9;
defparam \macro_inst|spi_inst|tx_en_r[1] .mask = 16'h3300;
defparam \macro_inst|spi_inst|tx_en_r[1] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[1] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[1] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[1] .BypassEn = 1'b1;
defparam \macro_inst|spi_inst|tx_en_r[1] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_en_r[2] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff~q ),
	.B(vcc),
	.C(\macro_inst|spi_inst|tx_en_r [1]),
	.D(\macro_inst|rx_fifo_req [0]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|tx_en_r [2]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X58_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y2_GND),
	.SyncReset(SyncReset_X58_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y2_VCC),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|tx_en_r [2]));
defparam \macro_inst|spi_inst|tx_en_r[2] .coord_x = 15;
defparam \macro_inst|spi_inst|tx_en_r[2] .coord_y = 3;
defparam \macro_inst|spi_inst|tx_en_r[2] .coord_z = 13;
defparam \macro_inst|spi_inst|tx_en_r[2] .mask = 16'hAA00;
defparam \macro_inst|spi_inst|tx_en_r[2] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[2] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[2] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[2] .BypassEn = 1'b1;
defparam \macro_inst|spi_inst|tx_en_r[2] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_en_r[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|spi_inst|tx_en_r [2]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|tx_en_r [3]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X58_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|tx_en_r[3]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|tx_en_r [3]));
defparam \macro_inst|spi_inst|tx_en_r[3] .coord_x = 15;
defparam \macro_inst|spi_inst|tx_en_r[3] .coord_y = 3;
defparam \macro_inst|spi_inst|tx_en_r[3] .coord_z = 7;
defparam \macro_inst|spi_inst|tx_en_r[3] .mask = 16'hFF00;
defparam \macro_inst|spi_inst|tx_en_r[3] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[3] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[3] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[3] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[3] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_en_r[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|spi_inst|tx_en_r [3]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|tx_en_r [4]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X58_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|tx_en_r[4]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|tx_en_r [4]));
defparam \macro_inst|spi_inst|tx_en_r[4] .coord_x = 15;
defparam \macro_inst|spi_inst|tx_en_r[4] .coord_y = 3;
defparam \macro_inst|spi_inst|tx_en_r[4] .coord_z = 8;
defparam \macro_inst|spi_inst|tx_en_r[4] .mask = 16'hFF00;
defparam \macro_inst|spi_inst|tx_en_r[4] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[4] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[4] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[4] .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[4] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_en_r[5] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|spi_inst|tx_en_r [4]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|spi_inst|tx_en_r [5]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X58_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y2_GND),
	.SyncReset(SyncReset_X58_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y2_VCC),
	.LutOut(slave_ahb_hwdata[23]),
	.Cout(),
	.Q(\macro_inst|spi_inst|tx_en_r [5]));
defparam \macro_inst|spi_inst|tx_en_r[5] .coord_x = 15;
defparam \macro_inst|spi_inst|tx_en_r[5] .coord_y = 3;
defparam \macro_inst|spi_inst|tx_en_r[5] .coord_z = 15;
defparam \macro_inst|spi_inst|tx_en_r[5] .mask = 16'h0000;
defparam \macro_inst|spi_inst|tx_en_r[5] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[5] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[5] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[5] .BypassEn = 1'b1;
defparam \macro_inst|spi_inst|tx_en_r[5] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_en_r[6] (
	.A(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|empty_dff~q ),
	.B(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_lsb~q ),
	.C(\macro_inst|spi_inst|tx_en_r [5]),
	.D(\macro_inst|rx_fifo_req [0]),
	.Cin(),
	.Qin(\macro_inst|spi_inst|tx_en_r [6]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X58_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y2_GND),
	.SyncReset(SyncReset_X58_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y2_VCC),
	.LutOut(\macro_inst|rx_fifo_inst|scfifo_component|auto_generated|dpfifo|_~9_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|tx_en_r [6]));
defparam \macro_inst|spi_inst|tx_en_r[6] .coord_x = 15;
defparam \macro_inst|spi_inst|tx_en_r[6] .coord_y = 3;
defparam \macro_inst|spi_inst|tx_en_r[6] .coord_z = 14;
defparam \macro_inst|spi_inst|tx_en_r[6] .mask = 16'h2200;
defparam \macro_inst|spi_inst|tx_en_r[6] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[6] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[6] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[6] .BypassEn = 1'b1;
defparam \macro_inst|spi_inst|tx_en_r[6] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_en_r[7] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|spi_inst|tx_en_r [6]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|spi_inst|tx_en_r [7]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X58_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y2_GND),
	.SyncReset(SyncReset_X58_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y2_VCC),
	.LutOut(slave_ahb_haddr[20]),
	.Cout(),
	.Q(\macro_inst|spi_inst|tx_en_r [7]));
defparam \macro_inst|spi_inst|tx_en_r[7] .coord_x = 15;
defparam \macro_inst|spi_inst|tx_en_r[7] .coord_y = 3;
defparam \macro_inst|spi_inst|tx_en_r[7] .coord_z = 4;
defparam \macro_inst|spi_inst|tx_en_r[7] .mask = 16'h0000;
defparam \macro_inst|spi_inst|tx_en_r[7] .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[7] .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[7] .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_en_r[7] .BypassEn = 1'b1;
defparam \macro_inst|spi_inst|tx_en_r[7] .CarryEnb = 1'b1;

alta_slice \macro_inst|spi_inst|tx_req (
	.A(\macro_inst|spi_inst|sck_cnt [2]),
	.B(\macro_inst|csen [0]),
	.C(\macro_inst|spi_inst|csen_r [0]),
	.D(\macro_inst|spi_inst|Equal0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|spi_inst|tx_req~q ),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X50_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X50_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|spi_inst|always1~0_combout ),
	.Cout(),
	.Q(\macro_inst|spi_inst|tx_req~q ));
defparam \macro_inst|spi_inst|tx_req .coord_x = 14;
defparam \macro_inst|spi_inst|tx_req .coord_y = 2;
defparam \macro_inst|spi_inst|tx_req .coord_z = 3;
defparam \macro_inst|spi_inst|tx_req .mask = 16'hAE0C;
defparam \macro_inst|spi_inst|tx_req .modeMux = 1'b0;
defparam \macro_inst|spi_inst|tx_req .FeedbackMux = 1'b0;
defparam \macro_inst|spi_inst|tx_req .ShiftMux = 1'b0;
defparam \macro_inst|spi_inst|tx_req .BypassEn = 1'b0;
defparam \macro_inst|spi_inst|tx_req .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_en[0] (
	.A(),
	.B(),
	.C(\macro_inst|tx_fifo_rdreq_r [0]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|tx_en [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X53_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X53_Y1_GND),
	.SyncReset(SyncReset_X53_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y1_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|tx_en [0]));
defparam \macro_inst|tx_en[0] .coord_x = 15;
defparam \macro_inst|tx_en[0] .coord_y = 4;
defparam \macro_inst|tx_en[0] .coord_z = 3;
defparam \macro_inst|tx_en[0] .mask = 16'hFFFF;
defparam \macro_inst|tx_en[0] .modeMux = 1'b1;
defparam \macro_inst|tx_en[0] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_en[0] .ShiftMux = 1'b0;
defparam \macro_inst|tx_en[0] .BypassEn = 1'b1;
defparam \macro_inst|tx_en[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_empty_r[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ),
	.Cin(),
	.Qin(\macro_inst|tx_fifo_empty_r [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X49_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X49_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_empty_r[0]~0_combout ),
	.Cout(),
	.Q(\macro_inst|tx_fifo_empty_r [0]));
defparam \macro_inst|tx_fifo_empty_r[0] .coord_x = 15;
defparam \macro_inst|tx_fifo_empty_r[0] .coord_y = 2;
defparam \macro_inst|tx_fifo_empty_r[0] .coord_z = 13;
defparam \macro_inst|tx_fifo_empty_r[0] .mask = 16'h00FF;
defparam \macro_inst|tx_fifo_empty_r[0] .modeMux = 1'b0;
defparam \macro_inst|tx_fifo_empty_r[0] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_empty_r[0] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_empty_r[0] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_empty_r[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_empty_r[1] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|tx_fifo_empty_r [0]),
	.D(\macro_inst|spi_inst|sck_cnt [4]),
	.Cin(\macro_inst|spi_inst|Add0~10 ),
	.Qin(\macro_inst|tx_fifo_empty_r [1]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X50_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X50_Y2_GND),
	.SyncReset(SyncReset_X50_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X50_Y2_VCC),
	.LutOut(\macro_inst|spi_inst|Add0~11_combout ),
	.Cout(),
	.Q(\macro_inst|tx_fifo_empty_r [1]));
defparam \macro_inst|tx_fifo_empty_r[1] .coord_x = 14;
defparam \macro_inst|tx_fifo_empty_r[1] .coord_y = 2;
defparam \macro_inst|tx_fifo_empty_r[1] .coord_z = 10;
defparam \macro_inst|tx_fifo_empty_r[1] .mask = 16'h0FF0;
defparam \macro_inst|tx_fifo_empty_r[1] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_empty_r[1] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_empty_r[1] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_empty_r[1] .BypassEn = 1'b1;
defparam \macro_inst|tx_fifo_empty_r[1] .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_empty_r[2] (
	.A(\macro_inst|spi_inst|sck_cnt [3]),
	.B(vcc),
	.C(\macro_inst|tx_fifo_empty_r [1]),
	.D(vcc),
	.Cin(\macro_inst|spi_inst|Add0~7 ),
	.Qin(\macro_inst|tx_fifo_empty_r [2]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X50_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X50_Y2_GND),
	.SyncReset(SyncReset_X50_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X50_Y2_VCC),
	.LutOut(\macro_inst|spi_inst|Add0~9_combout ),
	.Cout(\macro_inst|spi_inst|Add0~10 ),
	.Q(\macro_inst|tx_fifo_empty_r [2]));
defparam \macro_inst|tx_fifo_empty_r[2] .coord_x = 14;
defparam \macro_inst|tx_fifo_empty_r[2] .coord_y = 2;
defparam \macro_inst|tx_fifo_empty_r[2] .coord_z = 9;
defparam \macro_inst|tx_fifo_empty_r[2] .mask = 16'hA5AF;
defparam \macro_inst|tx_fifo_empty_r[2] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_empty_r[2] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_empty_r[2] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_empty_r[2] .BypassEn = 1'b1;
defparam \macro_inst|tx_fifo_empty_r[2] .CarryEnb = 1'b0;

alta_bram9k \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 (
	.DataInA({vcc, \macro_inst|apb_pwdata_r [7], \macro_inst|apb_pwdata_r [6], \macro_inst|apb_pwdata_r [5], \macro_inst|apb_pwdata_r [4], \macro_inst|apb_pwdata_r [3], \macro_inst|apb_pwdata_r [2], \macro_inst|apb_pwdata_r [1], \macro_inst|apb_pwdata_r [0], vcc, \macro_inst|apb_pwdata_r [7], \macro_inst|apb_pwdata_r [6], \macro_inst|apb_pwdata_r [5], \macro_inst|apb_pwdata_r [4], \macro_inst|apb_pwdata_r [3], \macro_inst|apb_pwdata_r [2], \macro_inst|apb_pwdata_r [1], \macro_inst|apb_pwdata_r [0]}),
	.DataInB({1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz}),
	.AddressA({\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0], vcc, vcc, vcc}),
	.AddressB({\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0], vcc, vcc, vcc}),
	.ByteEnA({vcc, vcc}),
	.ByteEnB({1'bz, 1'bz}),
	.DataOutA({\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [17], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [16], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [15], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [14], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [13], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [12], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [11], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [10], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [9], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [8], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [7], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [6], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [5], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [4], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [3], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [2], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [1], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutA [0]}),
	.DataOutB({\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [17], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [16], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [15], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [14], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [13], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [12], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [11], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [10], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [9], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [8], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [7], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [6], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [5], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [4], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [3], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [2], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [1], \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0__DataOutB [0]}),
	.Clk0(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn0(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.AsyncReset0(gnd),
	.Clk1(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ),
	.ClkEn1(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ),
	.AsyncReset1(gnd),
	.WeA(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.ReA(gnd),
	.WeB(gnd),
	.ReB(vcc),
	.AddressStallA(gnd),
	.AddressStallB(gnd));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .coord_x = 13;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .coord_y = 4;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .coord_z = 0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .CLKMODE = 2'b10;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .PACKEDMODE = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .PORTA_CLKIN_EN = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .PORTA_CLKOUT_EN = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .PORTB_CLKIN_EN = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .PORTB_CLKOUT_EN = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .PORTA_RSTIN_EN = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .PORTA_RSTOUT_EN = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .PORTB_RSTIN_EN = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .PORTB_RSTOUT_EN = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .PORTA_WIDTH = 5'b01000;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .PORTB_WIDTH = 5'b01000;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .PORTA_WRITETHRU = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .PORTB_WRITETHRU = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .PORTA_OUTREG = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .PORTB_OUTREG = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .RSEN_DLY = 2'b00;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .DLYTIME = 2'b00;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .INIT_VAL = 9216'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ),
	.B(\macro_inst|tx_fifo_wreq [0]),
	.C(\macro_inst|tx_fifo_rdreq [0]),
	.D(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 .coord_x = 15;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 .coord_z = 15;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 .mask = 16'hB444;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 .modeMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full (
	.A(\macro_inst|tx_fifo_rdreq [0]),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout ),
	.Cin(),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X49_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X49_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4_combout ),
	.Cout(),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full .coord_x = 15;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full .coord_z = 12;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full .mask = 16'hFF50;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full .modeMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full .FeedbackMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]),
	.B(\macro_inst|tx_fifo_wreq [0]),
	.C(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ),
	.D(\macro_inst|tx_fifo_rdreq [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 .coord_x = 16;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 .coord_z = 6;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 .mask = 16'h0080;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 .modeMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]),
	.C(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]),
	.D(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 .coord_x = 16;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 .coord_z = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 .mask = 16'h8000;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 .modeMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]),
	.C(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]),
	.D(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 .coord_x = 16;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 .coord_z = 10;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 .mask = 16'h8000;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 .modeMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout ),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout ),
	.C(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout ),
	.D(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 .coord_x = 16;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 .coord_z = 7;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 .mask = 16'h8000;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 .modeMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~4_combout ),
	.D(\macro_inst|tx_fifo_rdreq [0]),
	.Cin(),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X49_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X49_Y2_GND),
	.SyncReset(SyncReset_X49_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X49_Y2_VCC),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ),
	.Cout(),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty .coord_x = 15;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty .coord_z = 1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty .mask = 16'hF000;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty .modeMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty .FeedbackMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty .BypassEn = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ),
	.D(\macro_inst|tx_fifo_wreq [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 .coord_x = 16;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 .coord_z = 5;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 .mask = 16'hFFF0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 .modeMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]),
	.C(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]),
	.D(\macro_inst|tx_fifo_rdreq [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 .coord_x = 16;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 .coord_z = 11;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 .mask = 16'hFEFF;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 .modeMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]),
	.C(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]),
	.D(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 .coord_x = 16;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 .coord_z = 12;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 .mask = 16'hFFFE;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 .modeMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~3 (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout ),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]),
	.C(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]),
	.D(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~3 .coord_x = 16;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~3 .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~3 .coord_z = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~3 .mask = 16'hFFFB;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~3 .modeMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~3 .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~3 .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~3 .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~3 .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~4 (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~3_combout ),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout ),
	.C(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ),
	.D(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~4 .coord_x = 16;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~4 .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~4 .coord_z = 4;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~4 .mask = 16'hFFE0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~4 .modeMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~4 .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~4 .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~4 .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~4 .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout_X49_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X49_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] .coord_x = 15;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] .coord_z = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] .mask = 16'h3399;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout_X49_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X49_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] .coord_x = 15;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] .coord_z = 3;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] .mask = 16'h3C6F;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout_X49_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X49_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] .coord_x = 15;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] .coord_z = 4;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] .mask = 16'hC309;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout_X49_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X49_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] .coord_x = 15;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] .coord_z = 5;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] .mask = 16'h3C6F;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout_X49_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X49_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] .coord_x = 15;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] .coord_z = 6;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] .mask = 16'hC309;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout_X49_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X49_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] .coord_x = 15;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] .coord_z = 7;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] .mask = 16'h3C6F;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout_X49_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X49_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] .coord_x = 15;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] .coord_z = 8;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] .mask = 16'hC309;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout_X49_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X49_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] .coord_x = 15;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] .coord_z = 9;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] .mask = 16'h3C6F;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout_X49_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X49_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] .coord_x = 15;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] .coord_z = 10;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] .mask = 16'hC309;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout_X49_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X49_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~combout ),
	.Cout(),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] .coord_x = 15;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] .coord_y = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] .coord_z = 11;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] .mask = 16'h0FF0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout_X56_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] .coord_y = 7;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] .coord_z = 6;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] .mask = 16'h33CC;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout_X56_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] .coord_y = 7;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] .coord_z = 7;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] .mask = 16'h3C3F;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout_X56_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] .coord_y = 7;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] .coord_z = 8;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] .mask = 16'hC30C;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout_X56_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] .coord_y = 7;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] .coord_z = 9;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] .mask = 16'h3C3F;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout_X56_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] .coord_y = 7;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] .coord_z = 10;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] .mask = 16'hC30C;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout_X56_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] .coord_y = 7;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] .coord_z = 11;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] .mask = 16'h3C3F;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout_X56_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] .coord_y = 7;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] .coord_z = 12;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] .mask = 16'hC30C;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout_X56_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] .coord_y = 7;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] .coord_z = 13;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] .mask = 16'h3C3F;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout_X56_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] .coord_y = 7;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] .coord_z = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] .mask = 16'hC30C;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout_X56_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~combout ),
	.Cout(),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] .coord_y = 7;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] .coord_z = 15;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] .mask = 16'h3C3C;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .coord_y = 4;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .coord_z = 0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .mask = 16'h33CC;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .coord_y = 4;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .coord_z = 1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .mask = 16'h3C3F;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .coord_y = 4;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .coord_z = 2;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .mask = 16'hC30C;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .coord_y = 4;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .coord_z = 3;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .mask = 16'h3C3F;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .coord_y = 4;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .coord_z = 4;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .mask = 16'hC30C;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .coord_y = 4;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .coord_z = 5;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .mask = 16'h3C3F;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .coord_y = 4;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .coord_z = 6;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .mask = 16'hC30C;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .coord_y = 4;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .coord_z = 7;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .mask = 16'h3C3F;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] (
	.A(vcc),
	.B(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout ),
	.Cout(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT ),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .coord_y = 4;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .coord_z = 8;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .mask = 16'hC30C;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .CarryEnb = 1'b0;

alta_slice \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9]),
	.Cin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT ),
	.Qin(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk__macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout_X54_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout ),
	.Cout(),
	.Q(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9]));
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .coord_x = 14;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .coord_y = 4;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .coord_z = 9;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .mask = 16'h0FF0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .modeMux = 1'b1;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_rdreq[0] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|spi_inst|tx_req~q ),
	.D(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ),
	.Cin(),
	.Qin(\macro_inst|tx_fifo_rdreq [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X49_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X49_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|always3~0_combout ),
	.Cout(),
	.Q(\macro_inst|tx_fifo_rdreq [0]));
defparam \macro_inst|tx_fifo_rdreq[0] .coord_x = 15;
defparam \macro_inst|tx_fifo_rdreq[0] .coord_y = 2;
defparam \macro_inst|tx_fifo_rdreq[0] .coord_z = 0;
defparam \macro_inst|tx_fifo_rdreq[0] .mask = 16'hF000;
defparam \macro_inst|tx_fifo_rdreq[0] .modeMux = 1'b0;
defparam \macro_inst|tx_fifo_rdreq[0] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_rdreq[0] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_rdreq[0] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_rdreq[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_rdreq_r[0] (
	.A(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ),
	.B(vcc),
	.C(\macro_inst|tx_fifo_rdreq [0]),
	.D(\macro_inst|tx_fifo_wreq [0]),
	.Cin(),
	.Qin(\macro_inst|tx_fifo_rdreq_r [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X49_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X49_Y2_GND),
	.SyncReset(SyncReset_X49_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X49_Y2_VCC),
	.LutOut(\macro_inst|tx_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ),
	.Cout(),
	.Q(\macro_inst|tx_fifo_rdreq_r [0]));
defparam \macro_inst|tx_fifo_rdreq_r[0] .coord_x = 15;
defparam \macro_inst|tx_fifo_rdreq_r[0] .coord_y = 2;
defparam \macro_inst|tx_fifo_rdreq_r[0] .coord_z = 14;
defparam \macro_inst|tx_fifo_rdreq_r[0] .mask = 16'h5500;
defparam \macro_inst|tx_fifo_rdreq_r[0] .modeMux = 1'b0;
defparam \macro_inst|tx_fifo_rdreq_r[0] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_rdreq_r[0] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_rdreq_r[0] .BypassEn = 1'b1;
defparam \macro_inst|tx_fifo_rdreq_r[0] .CarryEnb = 1'b1;

alta_slice \macro_inst|tx_fifo_wreq[0] (
	.A(\macro_inst|ahb2apb_inst|paddr [15]),
	.B(\macro_inst|ahb2apb_inst|pwrite~q ),
	.C(\macro_inst|ahb2apb_inst|penable~q ),
	.D(\macro_inst|ahb2apb_inst|psel~q ),
	.Cin(),
	.Qin(\macro_inst|tx_fifo_wreq [0]),
	.Clk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk_X52_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X52_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|always1~0_combout ),
	.Cout(),
	.Q(\macro_inst|tx_fifo_wreq [0]));
defparam \macro_inst|tx_fifo_wreq[0] .coord_x = 15;
defparam \macro_inst|tx_fifo_wreq[0] .coord_y = 5;
defparam \macro_inst|tx_fifo_wreq[0] .coord_z = 3;
defparam \macro_inst|tx_fifo_wreq[0] .mask = 16'h4000;
defparam \macro_inst|tx_fifo_wreq[0] .modeMux = 1'b0;
defparam \macro_inst|tx_fifo_wreq[0] .FeedbackMux = 1'b0;
defparam \macro_inst|tx_fifo_wreq[0] .ShiftMux = 1'b0;
defparam \macro_inst|tx_fifo_wreq[0] .BypassEn = 1'b0;
defparam \macro_inst|tx_fifo_wreq[0] .CarryEnb = 1'b1;

alta_io_gclk \pll_inst|auto_generated|clk[3]~clkctrl (
	.inclk(\auto_generated_inst.hbo_22_7da7c782f7e09fdc_bp ),
	.outclk(\pll_inst|auto_generated|clk[3]~clkctrl_outclk ));
defparam \pll_inst|auto_generated|clk[3]~clkctrl .coord_x = 22;
defparam \pll_inst|auto_generated|clk[3]~clkctrl .coord_y = 4;
defparam \pll_inst|auto_generated|clk[3]~clkctrl .coord_z = 1;

alta_pllve \pll_inst|auto_generated|pll1 (
	.clkin(\PIN_HSE~input_o ),
	.clkfb(\pll_inst|auto_generated|pll1~FBOUT ),
	.pfden(vcc),
	.resetn(!\PLL_ENABLE~combout ),
	.phasecounterselect({gnd, gnd, gnd}),
	.phaseupdown(gnd),
	.phasestep(gnd),
	.scanclk(gnd),
	.scanclkena(vcc),
	.scandata(gnd),
	.configupdate(gnd),
	.scandataout(),
	.scandone(),
	.phasedone(),
	.clkout0(\pll_inst|auto_generated|pll1_CLK_bus [0]),
	.clkout1(\pll_inst|auto_generated|pll1_CLK_bus [1]),
	.clkout2(\pll_inst|auto_generated|pll1_CLK_bus [2]),
	.clkout3(\auto_generated_inst.hbo_22_7da7c782f7e09fdc_bp ),
	.clkout4(\pll_inst|auto_generated|pll1_CLK_bus [4]),
	.clkfbout(\pll_inst|auto_generated|pll1~FBOUT ),
	.lock(\auto_generated_inst.hbo_13_7ba00b93ceceb4ca_bp ));
defparam \pll_inst|auto_generated|pll1 .coord_x = 22;
defparam \pll_inst|auto_generated|pll1 .coord_y = 5;
defparam \pll_inst|auto_generated|pll1 .coord_z = 0;
defparam \pll_inst|auto_generated|pll1 .CLKIN_HIGH = 8'b11111111;
defparam \pll_inst|auto_generated|pll1 .CLKIN_LOW = 8'b11111111;
defparam \pll_inst|auto_generated|pll1 .CLKIN_TRIM = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKIN_BYPASS = 1'b1;
defparam \pll_inst|auto_generated|pll1 .CLKFB_HIGH = 8'b00011101;
defparam \pll_inst|auto_generated|pll1 .CLKFB_LOW = 8'b00011101;
defparam \pll_inst|auto_generated|pll1 .CLKFB_TRIM = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKFB_BYPASS = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKDIV0_EN = 1'b1;
defparam \pll_inst|auto_generated|pll1 .CLKDIV1_EN = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKDIV2_EN = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKDIV3_EN = 1'b1;
defparam \pll_inst|auto_generated|pll1 .CLKDIV4_EN = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_HIGH = 8'b00000010;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_LOW = 8'b00000010;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_TRIM = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_BYPASS = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_HIGH = 8'b11111111;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_LOW = 8'b11111111;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_TRIM = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_BYPASS = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_HIGH = 8'b11111111;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_LOW = 8'b11111111;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_TRIM = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_BYPASS = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_HIGH = 8'b00101111;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_LOW = 8'b00101111;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_TRIM = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_BYPASS = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_HIGH = 8'b11111111;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_LOW = 8'b11111111;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_TRIM = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_BYPASS = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_DEL = 8'b00000000;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_DEL = 8'b00000000;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_DEL = 8'b00000000;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_DEL = 8'b00000000;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_DEL = 8'b00000000;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_PHASE = 3'b000;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_PHASE = 3'b000;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_PHASE = 3'b000;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_PHASE = 3'b000;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_PHASE = 3'b000;
defparam \pll_inst|auto_generated|pll1 .CLKFB_DEL = 8'b00000000;
defparam \pll_inst|auto_generated|pll1 .CLKFB_PHASE = 3'b000;
defparam \pll_inst|auto_generated|pll1 .FEEDBACK_MODE = 3'b100;
defparam \pll_inst|auto_generated|pll1 .FBDELAY_VAL = 3'b100;
defparam \pll_inst|auto_generated|pll1 .PLLOUTP_EN = 1'b0;
defparam \pll_inst|auto_generated|pll1 .PLLOUTN_EN = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_CASCADE = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_CASCADE = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_CASCADE = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_CASCADE = 1'b0;
defparam \pll_inst|auto_generated|pll1 .VCO_POST_DIV = 1'b1;
defparam \pll_inst|auto_generated|pll1 .REG_CTRL = 2'b00;
defparam \pll_inst|auto_generated|pll1 .CP = 3'b100;
defparam \pll_inst|auto_generated|pll1 .RREF = 2'b01;
defparam \pll_inst|auto_generated|pll1 .RVI = 2'b01;
defparam \pll_inst|auto_generated|pll1 .IVCO = 3'b010;
defparam \pll_inst|auto_generated|pll1 .PLL_EN_FLAG = 1'b1;

alta_slice \pll_inst|auto_generated|pll_lock_sync (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\pll_inst|auto_generated|pll_lock_sync~q ),
	.Clk(\auto_generated_inst.hbo_13_7ba00b93ceceb4ca_bp_X48_Y2_SIG_VCC ),
	.AsyncReset(\PLL_ENABLE~clkctrl_outclk__AsyncReset_X48_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\pll_inst|auto_generated|pll_lock_sync~feeder_combout ),
	.Cout(),
	.Q(\pll_inst|auto_generated|pll_lock_sync~q ));
defparam \pll_inst|auto_generated|pll_lock_sync .coord_x = 16;
defparam \pll_inst|auto_generated|pll_lock_sync .coord_y = 2;
defparam \pll_inst|auto_generated|pll_lock_sync .coord_z = 13;
defparam \pll_inst|auto_generated|pll_lock_sync .mask = 16'hFFFF;
defparam \pll_inst|auto_generated|pll_lock_sync .modeMux = 1'b0;
defparam \pll_inst|auto_generated|pll_lock_sync .FeedbackMux = 1'b0;
defparam \pll_inst|auto_generated|pll_lock_sync .ShiftMux = 1'b0;
defparam \pll_inst|auto_generated|pll_lock_sync .BypassEn = 1'b0;
defparam \pll_inst|auto_generated|pll_lock_sync .CarryEnb = 1'b1;

alta_rv32 rv32(
	.sys_clk(\gclksw_inst|gclk_switch__alta_gclksw__clkout ),
	.mem_ahb_hready(\rv32.mem_ahb_hready ),
	.mem_ahb_hreadyout(!\macro_inst|ahb2apb_inst|hreadyout~q ),
	.mem_ahb_htrans({\rv32.mem_ahb_htrans[1] , \rv32.mem_ahb_htrans[0] }),
	.mem_ahb_hsize({\rv32.mem_ahb_hsize[2] , \rv32.mem_ahb_hsize[1] , \rv32.mem_ahb_hsize[0] }),
	.mem_ahb_hburst({\rv32.mem_ahb_hburst[2] , \rv32.mem_ahb_hburst[1] , \rv32.mem_ahb_hburst[0] }),
	.mem_ahb_hwrite(\rv32.mem_ahb_hwrite ),
	.mem_ahb_haddr({\rv32.mem_ahb_haddr[31] , \rv32.mem_ahb_haddr[30] , \rv32.mem_ahb_haddr[29] , \rv32.mem_ahb_haddr[28] , \rv32.mem_ahb_haddr[27] , \rv32.mem_ahb_haddr[26] , \rv32.mem_ahb_haddr[25] , \rv32.mem_ahb_haddr[24] , \rv32.mem_ahb_haddr[23] , \rv32.mem_ahb_haddr[22] , \rv32.mem_ahb_haddr[21] , \rv32.mem_ahb_haddr[20] , \rv32.mem_ahb_haddr[19] , \rv32.mem_ahb_haddr[18] , \rv32.mem_ahb_haddr[17] , \rv32.mem_ahb_haddr[16] , \rv32.mem_ahb_haddr[15] , \rv32.mem_ahb_haddr[14] , \rv32.mem_ahb_haddr[13] , \rv32.mem_ahb_haddr[12] , \rv32.mem_ahb_haddr[11] , \rv32.mem_ahb_haddr[10] , \rv32.mem_ahb_haddr[9] , \rv32.mem_ahb_haddr[8] , \rv32.mem_ahb_haddr[7] , \rv32.mem_ahb_haddr[6] , \rv32.mem_ahb_haddr[5] , \rv32.mem_ahb_haddr[4] , \rv32.mem_ahb_haddr[3] , \rv32.mem_ahb_haddr[2] , \rv32.mem_ahb_haddr[1] , \rv32.mem_ahb_haddr[0] }),
	.mem_ahb_hwdata({\rv32.mem_ahb_hwdata[31] , \rv32.mem_ahb_hwdata[30] , \rv32.mem_ahb_hwdata[29] , \rv32.mem_ahb_hwdata[28] , \rv32.mem_ahb_hwdata[27] , \rv32.mem_ahb_hwdata[26] , \rv32.mem_ahb_hwdata[25] , \rv32.mem_ahb_hwdata[24] , \rv32.mem_ahb_hwdata[23] , \rv32.mem_ahb_hwdata[22] , \rv32.mem_ahb_hwdata[21] , \rv32.mem_ahb_hwdata[20] , \rv32.mem_ahb_hwdata[19] , \rv32.mem_ahb_hwdata[18] , \rv32.mem_ahb_hwdata[17] , \rv32.mem_ahb_hwdata[16] , \rv32.mem_ahb_hwdata[15] , \rv32.mem_ahb_hwdata[14] , \rv32.mem_ahb_hwdata[13] , \rv32.mem_ahb_hwdata[12] , \rv32.mem_ahb_hwdata[11] , \rv32.mem_ahb_hwdata[10] , \rv32.mem_ahb_hwdata[9] , \rv32.mem_ahb_hwdata[8] , \rv32.mem_ahb_hwdata[7] , \rv32.mem_ahb_hwdata[6] , \rv32.mem_ahb_hwdata[5] , \rv32.mem_ahb_hwdata[4] , \rv32.mem_ahb_hwdata[3] , \rv32.mem_ahb_hwdata[2] , \rv32.mem_ahb_hwdata[1] , \rv32.mem_ahb_hwdata[0] }),
	.mem_ahb_hresp(gnd),
	.mem_ahb_hrdata({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, \macro_inst|ahb2apb_inst|prdata [9], \macro_inst|ahb2apb_inst|prdata [8], \macro_inst|ahb2apb_inst|prdata [7], \macro_inst|ahb2apb_inst|prdata [6], \macro_inst|ahb2apb_inst|prdata [5], \macro_inst|ahb2apb_inst|prdata [4], \macro_inst|ahb2apb_inst|prdata [3], \macro_inst|ahb2apb_inst|prdata [2], \macro_inst|ahb2apb_inst|prdata [1], \macro_inst|ahb2apb_inst|prdata [0]}),
	.slave_ahb_hsel(gnd),
	.slave_ahb_hready(vcc),
	.slave_ahb_hreadyout(\rv32.slave_ahb_hreadyout ),
	.slave_ahb_htrans({gnd, gnd}),
	.slave_ahb_hsize({gnd, gnd, gnd}),
	.slave_ahb_hburst({gnd, gnd, gnd}),
	.slave_ahb_hwrite(gnd),
	.slave_ahb_haddr({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.slave_ahb_hwdata({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.slave_ahb_hresp(\rv32.slave_ahb_hresp ),
	.slave_ahb_hrdata({\rv32.slave_ahb_hrdata[31] , \rv32.slave_ahb_hrdata[30] , \rv32.slave_ahb_hrdata[29] , \rv32.slave_ahb_hrdata[28] , \rv32.slave_ahb_hrdata[27] , \rv32.slave_ahb_hrdata[26] , \rv32.slave_ahb_hrdata[25] , \rv32.slave_ahb_hrdata[24] , \rv32.slave_ahb_hrdata[23] , \rv32.slave_ahb_hrdata[22] , \rv32.slave_ahb_hrdata[21] , \rv32.slave_ahb_hrdata[20] , \rv32.slave_ahb_hrdata[19] , \rv32.slave_ahb_hrdata[18] , \rv32.slave_ahb_hrdata[17] , \rv32.slave_ahb_hrdata[16] , \rv32.slave_ahb_hrdata[15] , \rv32.slave_ahb_hrdata[14] , \rv32.slave_ahb_hrdata[13] , \rv32.slave_ahb_hrdata[12] , \rv32.slave_ahb_hrdata[11] , \rv32.slave_ahb_hrdata[10] , \rv32.slave_ahb_hrdata[9] , \rv32.slave_ahb_hrdata[8] , \rv32.slave_ahb_hrdata[7] , \rv32.slave_ahb_hrdata[6] , \rv32.slave_ahb_hrdata[5] , \rv32.slave_ahb_hrdata[4] , \rv32.slave_ahb_hrdata[3] , \rv32.slave_ahb_hrdata[2] , \rv32.slave_ahb_hrdata[1] , \rv32.slave_ahb_hrdata[0] }),
	.gpio0_io_in({\PIN_23~input_o , \PIN_26~input_o , \PIN_33~input_o , \PIN_25~input_o , \PIN_47~input_o , \PIN_16~input_o , \PIN_43~input_o , \PIN_45~input_o }),
	.gpio0_io_out_data({\rv32.gpio0_io_out_data[7] , \rv32.gpio0_io_out_data[6] , \rv32.gpio0_io_out_data[5] , \rv32.gpio0_io_out_data[4] , \rv32.gpio0_io_out_data[3] , \rv32.gpio0_io_out_data[2] , \rv32.gpio0_io_out_data[1] , \rv32.gpio0_io_out_data[0] }),
	.gpio0_io_out_en({\rv32.gpio0_io_out_en[7] , \rv32.gpio0_io_out_en[6] , \rv32.gpio0_io_out_en[5] , \rv32.gpio0_io_out_en[4] , \rv32.gpio0_io_out_en[3] , \rv32.gpio0_io_out_en[2] , \rv32.gpio0_io_out_en[1] , \rv32.gpio0_io_out_en[0] }),
	.gpio1_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.gpio1_io_out_data({\rv32.gpio1_io_out_data[7] , \rv32.gpio1_io_out_data[6] , \rv32.gpio1_io_out_data[5] , \rv32.gpio1_io_out_data[4] , \rv32.gpio1_io_out_data[3] , \rv32.gpio1_io_out_data[2] , \rv32.gpio1_io_out_data[1] , \rv32.gpio1_io_out_data[0] }),
	.gpio1_io_out_en({\rv32.gpio1_io_out_en[7] , \rv32.gpio1_io_out_en[6] , \rv32.gpio1_io_out_en[5] , \rv32.gpio1_io_out_en[4] , \rv32.gpio1_io_out_en[3] , \rv32.gpio1_io_out_en[2] , \rv32.gpio1_io_out_en[1] , \rv32.gpio1_io_out_en[0] }),
	.sys_ctrl_clkSource({\rv32.sys_ctrl_clkSource[1] , \rv32.sys_ctrl_clkSource[0] }),
	.sys_ctrl_hseEnable(\rv32.sys_ctrl_hseEnable ),
	.sys_ctrl_hseBypass(\rv32.sys_ctrl_hseBypass ),
	.sys_ctrl_pllEnable(\rv32.sys_ctrl_pllEnable ),
	.sys_ctrl_pllReady(\auto_generated_inst.hbo_13_7ba00b93ceceb4ca_bp ),
	.sys_ctrl_sleep(\rv32.sys_ctrl_sleep ),
	.sys_ctrl_stop(\rv32.sys_ctrl_stop ),
	.sys_ctrl_standby(\rv32.sys_ctrl_standby ),
	.gpio2_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.gpio2_io_out_data({\rv32.gpio2_io_out_data[7] , \rv32.gpio2_io_out_data[6] , \rv32.gpio2_io_out_data[5] , \rv32.gpio2_io_out_data[4] , \rv32.gpio2_io_out_data[3] , \rv32.gpio2_io_out_data[2] , \rv32.gpio2_io_out_data[1] , \rv32.gpio2_io_out_data[0] }),
	.gpio2_io_out_en({\rv32.gpio2_io_out_en[7] , \rv32.gpio2_io_out_en[6] , \rv32.gpio2_io_out_en[5] , \rv32.gpio2_io_out_en[4] , \rv32.gpio2_io_out_en[3] , \rv32.gpio2_io_out_en[2] , \rv32.gpio2_io_out_en[1] , \rv32.gpio2_io_out_en[0] }),
	.gpio3_io_in({gnd, gnd, gnd, gnd, gnd, gnd, \PIN_36~input_o , \PIN_35~input_o }),
	.gpio3_io_out_data({\rv32.gpio3_io_out_data[7] , \rv32.gpio3_io_out_data[6] , \rv32.gpio3_io_out_data[5] , \rv32.gpio3_io_out_data[4] , \rv32.gpio3_io_out_data[3] , \rv32.gpio3_io_out_data[2] , \rv32.gpio3_io_out_data[1] , \rv32.gpio3_io_out_data[0] }),
	.gpio3_io_out_en({\rv32.gpio3_io_out_en[7] , \rv32.gpio3_io_out_en[6] , \rv32.gpio3_io_out_en[5] , \rv32.gpio3_io_out_en[4] , \rv32.gpio3_io_out_en[3] , \rv32.gpio3_io_out_en[2] , \rv32.gpio3_io_out_en[1] , \rv32.gpio3_io_out_en[0] }),
	.gpio4_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.gpio4_io_out_data({\rv32.gpio4_io_out_data[7] , \rv32.gpio4_io_out_data[6] , \rv32.gpio4_io_out_data[5] , \rv32.gpio4_io_out_data[4] , \rv32.gpio4_io_out_data[3] , \rv32.gpio4_io_out_data[2] , \rv32.gpio4_io_out_data[1] , \rv32.gpio4_io_out_data[0] }),
	.gpio4_io_out_en({\rv32.gpio4_io_out_en[7] , \rv32.gpio4_io_out_en[6] , \rv32.gpio4_io_out_en[5] , \rv32.gpio4_io_out_en[4] , \rv32.gpio4_io_out_en[3] , \rv32.gpio4_io_out_en[2] , \rv32.gpio4_io_out_en[1] , \rv32.gpio4_io_out_en[0] }),
	.gpio5_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, \PIN_54~input_o }),
	.gpio5_io_out_data({\rv32.gpio5_io_out_data[7] , \rv32.gpio5_io_out_data[6] , \rv32.gpio5_io_out_data[5] , \rv32.gpio5_io_out_data[4] , \rv32.gpio5_io_out_data[3] , \rv32.gpio5_io_out_data[2] , \rv32.gpio5_io_out_data[1] , \rv32.gpio5_io_out_data[0] }),
	.gpio5_io_out_en({\rv32.gpio5_io_out_en[7] , \rv32.gpio5_io_out_en[6] , \rv32.gpio5_io_out_en[5] , \rv32.gpio5_io_out_en[4] , \rv32.gpio5_io_out_en[3] , \rv32.gpio5_io_out_en[2] , \rv32.gpio5_io_out_en[1] , \rv32.gpio5_io_out_en[0] }),
	.gpio6_io_in({gnd, \PIN_41~input_o , \PIN_37~input_o , \PIN_38~input_o , gnd, \PIN_39~input_o , \PIN_53~input_o , \PIN_40~input_o }),
	.gpio6_io_out_data({\rv32.gpio6_io_out_data[7] , \rv32.gpio6_io_out_data[6] , \rv32.gpio6_io_out_data[5] , \rv32.gpio6_io_out_data[4] , \rv32.gpio6_io_out_data[3] , \rv32.gpio6_io_out_data[2] , \rv32.gpio6_io_out_data[1] , \rv32.gpio6_io_out_data[0] }),
	.gpio6_io_out_en({\rv32.gpio6_io_out_en[7] , \rv32.gpio6_io_out_en[6] , \rv32.gpio6_io_out_en[5] , \rv32.gpio6_io_out_en[4] , \rv32.gpio6_io_out_en[3] , \rv32.gpio6_io_out_en[2] , \rv32.gpio6_io_out_en[1] , \rv32.gpio6_io_out_en[0] }),
	.gpio7_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.gpio7_io_out_data({\rv32.gpio7_io_out_data[7] , \rv32.gpio7_io_out_data[6] , \rv32.gpio7_io_out_data[5] , \rv32.gpio7_io_out_data[4] , \rv32.gpio7_io_out_data[3] , \rv32.gpio7_io_out_data[2] , \rv32.gpio7_io_out_data[1] , \rv32.gpio7_io_out_data[0] }),
	.gpio7_io_out_en({\rv32.gpio7_io_out_en[7] , \rv32.gpio7_io_out_en[6] , \rv32.gpio7_io_out_en[5] , \rv32.gpio7_io_out_en[4] , \rv32.gpio7_io_out_en[3] , \rv32.gpio7_io_out_en[2] , \rv32.gpio7_io_out_en[1] , \rv32.gpio7_io_out_en[0] }),
	.gpio8_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.gpio8_io_out_data({\rv32.gpio8_io_out_data[7] , \rv32.gpio8_io_out_data[6] , \rv32.gpio8_io_out_data[5] , \rv32.gpio8_io_out_data[4] , \rv32.gpio8_io_out_data[3] , \rv32.gpio8_io_out_data[2] , \rv32.gpio8_io_out_data[1] , \rv32.gpio8_io_out_data[0] }),
	.gpio8_io_out_en({\rv32.gpio8_io_out_en[7] , \rv32.gpio8_io_out_en[6] , \rv32.gpio8_io_out_en[5] , \rv32.gpio8_io_out_en[4] , \rv32.gpio8_io_out_en[3] , \rv32.gpio8_io_out_en[2] , \rv32.gpio8_io_out_en[1] , \rv32.gpio8_io_out_en[0] }),
	.gpio9_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.gpio9_io_out_data({\rv32.gpio9_io_out_data[7] , \rv32.gpio9_io_out_data[6] , \rv32.gpio9_io_out_data[5] , \rv32.gpio9_io_out_data[4] , \rv32.gpio9_io_out_data[3] , \rv32.gpio9_io_out_data[2] , \rv32.gpio9_io_out_data[1] , \rv32.gpio9_io_out_data[0] }),
	.gpio9_io_out_en({\rv32.gpio9_io_out_en[7] , \rv32.gpio9_io_out_en[6] , \rv32.gpio9_io_out_en[5] , \rv32.gpio9_io_out_en[4] , \rv32.gpio9_io_out_en[3] , \rv32.gpio9_io_out_en[2] , \rv32.gpio9_io_out_en[1] , \rv32.gpio9_io_out_en[0] }),
	.ext_resetn(vcc),
	.resetn_out(\rv32.resetn_out ),
	.dmactive(\rv32.dmactive ),
	.swj_JTAGNSW(\rv32.swj_JTAGNSW ),
	.swj_JTAGSTATE({\rv32.swj_JTAGSTATE[3] , \rv32.swj_JTAGSTATE[2] , \rv32.swj_JTAGSTATE[1] , \rv32.swj_JTAGSTATE[0] }),
	.swj_JTAGIR({\rv32.swj_JTAGIR[3] , \rv32.swj_JTAGIR[2] , \rv32.swj_JTAGIR[1] , \rv32.swj_JTAGIR[0] }),
	.ext_int({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.ext_dma_DMACBREQ({gnd, gnd, gnd, gnd}),
	.ext_dma_DMACLBREQ({gnd, gnd, gnd, gnd}),
	.ext_dma_DMACSREQ({gnd, gnd, gnd, gnd}),
	.ext_dma_DMACLSREQ({gnd, gnd, gnd, gnd}),
	.ext_dma_DMACCLR({\rv32.ext_dma_DMACCLR[3] , \rv32.ext_dma_DMACCLR[2] , \rv32.ext_dma_DMACCLR[1] , \rv32.ext_dma_DMACCLR[0] }),
	.ext_dma_DMACTC({\rv32.ext_dma_DMACTC[3] , \rv32.ext_dma_DMACTC[2] , \rv32.ext_dma_DMACTC[1] , \rv32.ext_dma_DMACTC[0] }),
	.local_int({gnd, gnd, gnd, gnd}),
	.test_mode({gnd, gnd}),
	.usb0_xcvr_clk(gnd),
	.usb0_id(vcc));
defparam rv32.coord_x = 0;
defparam rv32.coord_y = 5;
defparam rv32.coord_z = 0;

alta_syncctrl syncload_ctrl_X49_Y2(
	.Din(),
	.Dout(SyncLoad_X49_Y2_VCC));
defparam syncload_ctrl_X49_Y2.coord_x = 15;
defparam syncload_ctrl_X49_Y2.coord_y = 2;
defparam syncload_ctrl_X49_Y2.coord_z = 1;
defparam syncload_ctrl_X49_Y2.SyncCtrlMux = 2'b01;

alta_syncctrl syncload_ctrl_X50_Y2(
	.Din(),
	.Dout(SyncLoad_X50_Y2_VCC));
defparam syncload_ctrl_X50_Y2.coord_x = 14;
defparam syncload_ctrl_X50_Y2.coord_y = 2;
defparam syncload_ctrl_X50_Y2.coord_z = 1;
defparam syncload_ctrl_X50_Y2.SyncCtrlMux = 2'b01;

alta_syncctrl syncload_ctrl_X51_Y1(
	.Din(),
	.Dout(SyncLoad_X51_Y1_VCC));
defparam syncload_ctrl_X51_Y1.coord_x = 17;
defparam syncload_ctrl_X51_Y1.coord_y = 3;
defparam syncload_ctrl_X51_Y1.coord_z = 1;
defparam syncload_ctrl_X51_Y1.SyncCtrlMux = 2'b01;

alta_syncctrl syncload_ctrl_X52_Y1(
	.Din(),
	.Dout(SyncLoad_X52_Y1_VCC));
defparam syncload_ctrl_X52_Y1.coord_x = 16;
defparam syncload_ctrl_X52_Y1.coord_y = 3;
defparam syncload_ctrl_X52_Y1.coord_z = 1;
defparam syncload_ctrl_X52_Y1.SyncCtrlMux = 2'b01;

alta_syncctrl syncload_ctrl_X52_Y2(
	.Din(),
	.Dout(SyncLoad_X52_Y2_VCC));
defparam syncload_ctrl_X52_Y2.coord_x = 15;
defparam syncload_ctrl_X52_Y2.coord_y = 5;
defparam syncload_ctrl_X52_Y2.coord_z = 1;
defparam syncload_ctrl_X52_Y2.SyncCtrlMux = 2'b01;

alta_syncctrl syncload_ctrl_X53_Y1(
	.Din(),
	.Dout(SyncLoad_X53_Y1_VCC));
defparam syncload_ctrl_X53_Y1.coord_x = 15;
defparam syncload_ctrl_X53_Y1.coord_y = 4;
defparam syncload_ctrl_X53_Y1.coord_z = 1;
defparam syncload_ctrl_X53_Y1.SyncCtrlMux = 2'b01;

alta_syncctrl syncload_ctrl_X53_Y2(
	.Din(),
	.Dout(SyncLoad_X53_Y2_VCC));
defparam syncload_ctrl_X53_Y2.coord_x = 14;
defparam syncload_ctrl_X53_Y2.coord_y = 6;
defparam syncload_ctrl_X53_Y2.coord_z = 1;
defparam syncload_ctrl_X53_Y2.SyncCtrlMux = 2'b01;

alta_syncctrl syncload_ctrl_X54_Y1(
	.Din(),
	.Dout(SyncLoad_X54_Y1_VCC));
defparam syncload_ctrl_X54_Y1.coord_x = 14;
defparam syncload_ctrl_X54_Y1.coord_y = 4;
defparam syncload_ctrl_X54_Y1.coord_z = 1;
defparam syncload_ctrl_X54_Y1.SyncCtrlMux = 2'b01;

alta_syncctrl syncload_ctrl_X54_Y2(
	.Din(),
	.Dout(SyncLoad_X54_Y2_VCC));
defparam syncload_ctrl_X54_Y2.coord_x = 14;
defparam syncload_ctrl_X54_Y2.coord_y = 3;
defparam syncload_ctrl_X54_Y2.coord_z = 1;
defparam syncload_ctrl_X54_Y2.SyncCtrlMux = 2'b01;

alta_syncctrl syncload_ctrl_X56_Y1(
	.Din(),
	.Dout(SyncLoad_X56_Y1_VCC));
defparam syncload_ctrl_X56_Y1.coord_x = 14;
defparam syncload_ctrl_X56_Y1.coord_y = 7;
defparam syncload_ctrl_X56_Y1.coord_z = 1;
defparam syncload_ctrl_X56_Y1.SyncCtrlMux = 2'b01;

alta_syncctrl syncload_ctrl_X56_Y2(
	.Din(),
	.Dout(SyncLoad_X56_Y2_VCC));
defparam syncload_ctrl_X56_Y2.coord_x = 14;
defparam syncload_ctrl_X56_Y2.coord_y = 8;
defparam syncload_ctrl_X56_Y2.coord_z = 1;
defparam syncload_ctrl_X56_Y2.SyncCtrlMux = 2'b01;

alta_syncctrl syncload_ctrl_X57_Y2(
	.Din(),
	.Dout(SyncLoad_X57_Y2_VCC));
defparam syncload_ctrl_X57_Y2.coord_x = 15;
defparam syncload_ctrl_X57_Y2.coord_y = 6;
defparam syncload_ctrl_X57_Y2.coord_z = 1;
defparam syncload_ctrl_X57_Y2.SyncCtrlMux = 2'b01;

alta_syncctrl syncload_ctrl_X58_Y2(
	.Din(),
	.Dout(SyncLoad_X58_Y2_VCC));
defparam syncload_ctrl_X58_Y2.coord_x = 15;
defparam syncload_ctrl_X58_Y2.coord_y = 3;
defparam syncload_ctrl_X58_Y2.coord_z = 1;
defparam syncload_ctrl_X58_Y2.SyncCtrlMux = 2'b01;

alta_syncctrl syncreset_ctrl_X49_Y2(
	.Din(),
	.Dout(SyncReset_X49_Y2_GND));
defparam syncreset_ctrl_X49_Y2.coord_x = 15;
defparam syncreset_ctrl_X49_Y2.coord_y = 2;
defparam syncreset_ctrl_X49_Y2.coord_z = 0;
defparam syncreset_ctrl_X49_Y2.SyncCtrlMux = 2'b00;

alta_syncctrl syncreset_ctrl_X50_Y2(
	.Din(),
	.Dout(SyncReset_X50_Y2_GND));
defparam syncreset_ctrl_X50_Y2.coord_x = 14;
defparam syncreset_ctrl_X50_Y2.coord_y = 2;
defparam syncreset_ctrl_X50_Y2.coord_z = 0;
defparam syncreset_ctrl_X50_Y2.SyncCtrlMux = 2'b00;

alta_syncctrl syncreset_ctrl_X51_Y1(
	.Din(),
	.Dout(SyncReset_X51_Y1_GND));
defparam syncreset_ctrl_X51_Y1.coord_x = 17;
defparam syncreset_ctrl_X51_Y1.coord_y = 3;
defparam syncreset_ctrl_X51_Y1.coord_z = 0;
defparam syncreset_ctrl_X51_Y1.SyncCtrlMux = 2'b00;

alta_syncctrl syncreset_ctrl_X52_Y1(
	.Din(),
	.Dout(SyncReset_X52_Y1_GND));
defparam syncreset_ctrl_X52_Y1.coord_x = 16;
defparam syncreset_ctrl_X52_Y1.coord_y = 3;
defparam syncreset_ctrl_X52_Y1.coord_z = 0;
defparam syncreset_ctrl_X52_Y1.SyncCtrlMux = 2'b00;

alta_syncctrl syncreset_ctrl_X52_Y2(
	.Din(),
	.Dout(SyncReset_X52_Y2_GND));
defparam syncreset_ctrl_X52_Y2.coord_x = 15;
defparam syncreset_ctrl_X52_Y2.coord_y = 5;
defparam syncreset_ctrl_X52_Y2.coord_z = 0;
defparam syncreset_ctrl_X52_Y2.SyncCtrlMux = 2'b00;

alta_syncctrl syncreset_ctrl_X53_Y1(
	.Din(),
	.Dout(SyncReset_X53_Y1_GND));
defparam syncreset_ctrl_X53_Y1.coord_x = 15;
defparam syncreset_ctrl_X53_Y1.coord_y = 4;
defparam syncreset_ctrl_X53_Y1.coord_z = 0;
defparam syncreset_ctrl_X53_Y1.SyncCtrlMux = 2'b00;

alta_syncctrl syncreset_ctrl_X53_Y2(
	.Din(),
	.Dout(SyncReset_X53_Y2_GND));
defparam syncreset_ctrl_X53_Y2.coord_x = 14;
defparam syncreset_ctrl_X53_Y2.coord_y = 6;
defparam syncreset_ctrl_X53_Y2.coord_z = 0;
defparam syncreset_ctrl_X53_Y2.SyncCtrlMux = 2'b00;

alta_syncctrl syncreset_ctrl_X54_Y1(
	.Din(),
	.Dout(SyncReset_X54_Y1_GND));
defparam syncreset_ctrl_X54_Y1.coord_x = 14;
defparam syncreset_ctrl_X54_Y1.coord_y = 4;
defparam syncreset_ctrl_X54_Y1.coord_z = 0;
defparam syncreset_ctrl_X54_Y1.SyncCtrlMux = 2'b00;

alta_syncctrl syncreset_ctrl_X54_Y2(
	.Din(),
	.Dout(SyncReset_X54_Y2_GND));
defparam syncreset_ctrl_X54_Y2.coord_x = 14;
defparam syncreset_ctrl_X54_Y2.coord_y = 3;
defparam syncreset_ctrl_X54_Y2.coord_z = 0;
defparam syncreset_ctrl_X54_Y2.SyncCtrlMux = 2'b00;

alta_syncctrl syncreset_ctrl_X56_Y1(
	.Din(),
	.Dout(SyncReset_X56_Y1_GND));
defparam syncreset_ctrl_X56_Y1.coord_x = 14;
defparam syncreset_ctrl_X56_Y1.coord_y = 7;
defparam syncreset_ctrl_X56_Y1.coord_z = 0;
defparam syncreset_ctrl_X56_Y1.SyncCtrlMux = 2'b00;

alta_syncctrl syncreset_ctrl_X56_Y2(
	.Din(),
	.Dout(SyncReset_X56_Y2_GND));
defparam syncreset_ctrl_X56_Y2.coord_x = 14;
defparam syncreset_ctrl_X56_Y2.coord_y = 8;
defparam syncreset_ctrl_X56_Y2.coord_z = 0;
defparam syncreset_ctrl_X56_Y2.SyncCtrlMux = 2'b00;

alta_syncctrl syncreset_ctrl_X57_Y2(
	.Din(),
	.Dout(SyncReset_X57_Y2_GND));
defparam syncreset_ctrl_X57_Y2.coord_x = 15;
defparam syncreset_ctrl_X57_Y2.coord_y = 6;
defparam syncreset_ctrl_X57_Y2.coord_z = 0;
defparam syncreset_ctrl_X57_Y2.SyncCtrlMux = 2'b00;

alta_syncctrl syncreset_ctrl_X58_Y2(
	.Din(),
	.Dout(SyncReset_X58_Y2_GND));
defparam syncreset_ctrl_X58_Y2.coord_x = 15;
defparam syncreset_ctrl_X58_Y2.coord_y = 3;
defparam syncreset_ctrl_X58_Y2.coord_z = 0;
defparam syncreset_ctrl_X58_Y2.SyncCtrlMux = 2'b00;

alta_slice sys_resetn(
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\rv32.resetn_out ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\sys_resetn~combout ),
	.Cout(),
	.Q());
defparam sys_resetn.coord_x = 14;
defparam sys_resetn.coord_y = 5;
defparam sys_resetn.coord_z = 7;
defparam sys_resetn.mask = 16'h00FF;
defparam sys_resetn.modeMux = 1'b0;
defparam sys_resetn.FeedbackMux = 1'b0;
defparam sys_resetn.ShiftMux = 1'b0;
defparam sys_resetn.BypassEn = 1'b0;
defparam sys_resetn.CarryEnb = 1'b1;

endmodule
